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| ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? 1 ? ? ? ? ? ? device highlights high performance pci controller ? 33/66 mhz 32-bit pci target ? zero-wait state pci target provides up to 264 mbps transfer rates ? target interface supports retry, disconnect with/without data transfer, and target abort ? fully programmable back-end interface ? independent pci bus (33/66 mhz) and local bus (up to 160 mhz) clocks ? fully customizable pci configuration space ? configurable fifos with depths up to 256 words ? reference design with driver code (win 95/98/2000/nt 4.0) available ? pci v2.3 compliant ? supports type 0 configuration cycles ? 3.3 v pci signaling ? 1.8 v supply voltage ? 484-ball pbga, 280-ball lfbga, 208-pin pqfp, 196-ball tfbga, and 144 -pin tqfp packages ? unlimited/continuous burst transfers supported extendable pci functionality ? support for configuration space from 0 40 to 0 3ff ? pci v2.3 power manage ment spec. compatible ? pci v2.3 vital product data (vpd) configuration support flexible programmable logic ? up to 1,478 logic cells ? up to 50,688 ram bits ? up to 264 i/o pins ? all back-end interface and glue-logic can be implemented on chip ? two 32-bit busses interface between the pci controller and the programmable logic ? up to twenty-two 2,304 bit dual-port high performance sram blocks ? up to 3,748 flip-flops available figure 1: ql58x0 block diagram pci bu s pci bu s 33/66 mhz/32 bit s (data and addre ss ) tar g et controller 160 mhz fifo s confi g . space hi g h speed lo g ic cell s hi g h speed data path pro g rammable lo g ic 32-bit interface pci controller 264 u s er i/o 33 /66 mhz/ 3 2-bit pci target with embedded programmable logic, embedded comput ational units, and dual port s ram ql58x0 enhanced quickpci? target family data s heet
www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 2 architecture overview the ql58x0 device family of quickp ci embedded standard products (esps) provides a complete and customizable pci interface solution combined with programmable logic. since the ql58x0 devices provide optimized pre-verified pci cores, the burden of pci timing closure and pci protocol compliance has been eliminated and allows for the maximu m 32-bit pci bus bandwidth (264 mbps). the programmable logic portion of this family contai ns up to 1,478 quicklogic logic cells and up to 22 quicklogic dual-port ram blocks. these configurable ram blocks can be configured in many width/depth combinations. they can also be combined with logic cell s to form fifos, or be initialized via serial eeprom on power-up and used as roms. the ql58x0 device meets pci 2.3 electrical and timing specifications and has been fully hardware-tested. the ql58x0 device features 1.8 v operatio n with multi-volt compatible i/os. the device can easily operate in 3.3 v embedded systems and is fully co mpatible with 3.3 v applications. pci controller the pci controller is a 33/66 mhz 32-bit pci 2.3 compliant target controller capable of infinite length target write and read transactions at zero wait states (264 mbps). the target interface offers full pci configuration space and flexible target addressi ng. it supports zero-wait- state target write and read operations. it also supports retry, disconnect wi th/without data transfer, and target abort requested by the back end. any number of 32-bi t bars may be configured as either memory or i/o space. all required and optional pci 2.3 configurat ion space registers can be implemented within the programmable region of the device. a reference design of a target configuration space and addressing module is available and is included in the quickworks? design software. the interface ports are designed for target transactions. the target configuration space and address decoding are done in the programmable logic region of the device. these functions are not timing critical, so leaving these elements in the programmable region allows the greatest degree of fl exibility to the designer. table 1 shows several commonly implemented ip cores in the programmable logic portion of the target controller device. their respective logic cell utilization and performance information are shown for easy reference. notice that the configuration space and addres s decoding core is labelled as an essential ip core. this ip block is necessary for the target controller to be fully functional. the optional ip cores are common interface ip cores made available so that designers may implement according to their design requirements. these optional ip cores do not affect the functionality of the target controller. ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 3 configuration s pace and address decode the configuration space is completely customizable in the programmable region of the device. pci address and command decoding is performed by lo gic in the programmable sect ion of the device. this allows support for any size of memory or i/o space for back end logic. it also al lows the user to implement any subset of the pci commands su pported by the ql58x0. quicklogic provides a reference address register/counter and command decode block. pci interface s ymbol figure 2 shows the graphical interface symbol numbers you ha ve to use in your schematic design in order to attach the local interface programmabl e logic design to the target pci core. if you are designing with a top- level verilog or vhdl file, use a structural instantiati on of this pci32tv2 block in stead of a graphical symbol. table 1: ip implemented in programmable logic essential pci ip cores logic cells ram performance configuration space/address decoding 110 n/a 33/66 mhz optional ip cores logic cells ram performance async 32x32 fifo 64 2 210 mhz async 128x32 fifo 88 2 190 mhz sdram controller 149 n/a 160 mhz ddr sdram controller 216 n/a 100 mhz pulse width modulation 20 n/a 303 mhz www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 4 figure 2: pci interface symbol ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 5 pci target interface table 2: pci target interface s ignal i/o description usr_addr_wrdata[31:0] o target address, and target write data. during all target accesses, the address is presented on usr_addr_wrdata[31:0]; at the same time, usr_adr_valid is active. during target write transactions, this port also presents valid write data to the pci configuration space or user logic when usr_adr_inc is active. usr_cbe[3:0] o pci command and byte enables. during target accesses, the pci command is presented on usr_cbe[3:0]; at the same time, usr_adr_valid is active. this port also presents active-low byte enables to the pci configuration space or user logic. usr_adr_valid o indicates the beginning of a pci transaction, and that a target address is valid on usr_addr_wrdata[31:0] and the pci command is valid on usr_cbe[3:0]. when this signal is active, the target address must be latched and decoded to determine if this address belongs to the device's memory or i/o space. also, the pci command must be decoded to determine the type of pci trans action. on subsequent clocks of a target access, this signal is low, indicating that address is not present on usr_addr_wrdata[31:0]. usr_adr_inc o indicates that the target address should be incremented, because the previous data transfer has completed. during burst tar get accesses, the target address is only presented to the back-end logic at the beginning of the transaction (when usr_adr_valid is active), and must therefor e be latched and incremented by four for subsequent data transfers. note that duri ng target write transactions, usr_adr_inc indicates valid data on usr_addr_wrdata[31:0] that must be accepted by the backend logic (regardless of the state of usr_rdy) . during read transactions, usr_adr_inc signals to the backend that the pci core has presented the read data on the pci bus (trdyn asserted). usr_rddecode i this signal should be the combinatorial decode of the ?user read? command from usr_cbe[3:0]. this command may be mapped from any of the pci read commands, such as memory read, memory read line, memory read multiple, i/o read, etc. it is internally gated with usr_adr_valid. usr_wrdecode i this signal should be the combinatorial de code of the ?user write? command from usr_cbe[3:0]. this command may be mapped from any of the pci write commands, such as memory write or i/o write. it is internally gated with usr_adr_valid. usr_select i this signal should be driven active when the address on usr_ad dr_wrdata[31:0] has been decoded and determined to be within the address space of the device. usr_addr_wrdata[31:0] must be compared to each of the valid base address registers in the pci config uration space. also, this signal must be gated by the memory access enable or i/o access enable registers in the pci configuration space (command register bits 1 or 0 at offset 04h). internally gated with usr_adr_valid. usr_write o this signal is active throughout a ?user write? transaction, which has been decoded by usr_wrdecode at the beginning of the tr ansaction. the write strobe for individual dwords of data (on usr_addr_wrdata[31:0]) during a user write transaction should be generated by logically anding this signal with usr_adr_inc. cfg_write o this signal is active throughout a ?configur ation write? transaction. the write strobe for individual dwords of data (on usr_ad dr_wrdata[31:0]) during a configuration write transaction should be generated by logically anding this signal with usr_adr_inc. cfg_rddata[31:0] i data from the pci configuration register s, required to be presented during pci configuration reads. www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 6 usr_rddata[31:0] i data from the back-end user logic required to be presented during pci user reads. cfg_cmdreg6 i bit 6 from the command register in the pc i configuration space (offset 04h). parity error response. if high, the core uses pe rrn to report data parity errors. otherwise it never drives it. cfg_cmdreg8 i bit 8 from the command register in the pci configuration space (offset 04h). serrn enable. if high, the cores uses serrn to report address parity errors if cfg_cmdreg6 is high. cfg_perr_det o parity error detected on the pci bus. when th is signal is active, bit 15 of the status register must be set in the pci configuration space (offset 04h). cfg_serr_sig o system error asserted on the pci bus. when this signal is active, the signalled system error bit, bit 14 of the status regi ster, must be set in the pci configuration space (offset 04h). usr_trdy o inverted copy of the trdyn signal as driven by the pci target interface. valid only within a target access. usr_devsel o inverted copy of the devseln signal as driven by the pci target interface. valid only within a target access. usr_last_cycle_d1 o active one clock cycle after the last data phase (may not with data transfer) occurs on pci and inactive one clock cycle afterwards. usr_rdy i used to delay (add wait states to) a tar get pci transaction when the backend needs additional time to provide data (read) or accept data (write). subject to pci latency restrictions. usr_stop i used to prematurely stop a pci target access on the next pci clock. usr_stopn o copy of the stopn signal as driven by the pci target interface usr_rdpipe_stat[1:0] o indicates the number of dwords currently in the read pipeline (?00? = 0 elements, ?01? = 1 element, ?11? = 2 elements). this value is important at the end of a transaction (i.e., when usr_last_cycle_d1 is active) if non-prefetchable memory is being read. non-prefetchable memory is defined as registers or memory elements whose value changes when they are read. examples are status registers which are cleared when they are read, or fifo memories, since co nsecutive reads from the same address in these elements may not produce the same data values. table 2: pci target interface (continued) s ignal i/o description ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 7 pci internal s ignals note: all devices support 33 mhz and 66 mhz pci except ql5840-pq208 which supports 33 mhz pci only. table 3: pci internal signals s ignal i/o description pci_clock o pci clock. pci_reset o pci reset signal. pci_irdyn_d1 o copy of the irdyn signal from the pci bus, delayed by one clock. pci_framen_d1 o copy of the framen signal from the pci bus, delayed by one clock. pci_devseln_d1 o copy of the devseln signal from t he pci bus, delayed by one clock. pci_trdyn_d1 o copy of the trdyn signal from the pci bus, delayed by one clock. pci_stopn_d1 o copy of the stopn signal from the pci bus, delayed by one clock. pci_idsel_d1 o copy of the idsel signal from the pci bus, delayed by one clock. table 4: ql58x0 target quickpci family members ql5810 ql5820 ql5840 max gates 63,840 188,946 320,640 logic cells 192 575 1,472 max flip-flops 630 1,455 3,748 max i/o 78 97 264 ram modules 2 14 22 ram bits 4,608 32,256 50,688 plls - - 4 ecus - - 12 packages tqfp 144 144 - tfbga (0.8 mm) 196 196 - pqfp - 208 208 lfbga (0.8 mm) - 280 280 pbga (1.0 mm) - - 484 table 5: max i/o per device/package combination device 144 tqfp 196 tfbga 208 pqfp 280 lfbga 484 pbga ql5810 54 78 - - - ql5820 54 78 97 117 - ql5840 - - 69 117 264 www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 8 quickworks design s oftware the quickworks package provides the most complete esp and fpga software solution from design entry to logic synthesis, to place and route, to power calculation, and simulation. the package provides a solution for designers who use third-party tools from cadence, mentor, orcad, synopsys, viewlogic, and other third- party tools for design entry, synthesis, or simulation. process data the ql58x0 device family is fabricated on a 0.18 , six layer metal cmos process. the core voltage is 1.8 v and the i/os are up to 3.3 v drive/tolerant. the ql58x0 device family product line is available in commercial, industrial, and military temperature grades. programmable logic architectural overview the ql58x0 device family logic cell structure is presented in figure 3 . this architectural feature addresses today's register-intensive designs. table 6: device speed grade and operating range a package availability a. c = commercial i = industrial m = military device 144 tqfp 196 tfbga 208 pqfp 280 lfbga 484 pbga ql5810 33a (c, i, & m) 33b (c, i, & m) 66c (c & i) 33a (c, i, & m) 33b (c, i, & m) 66c (c & i) --- ql5820 33a (c, i, & m) 33b (c, i, & m) 66c (c & i) 33a (c, i, & m) 33b (c, i, & m) 66c (c, i, & m) 33a (c, i, & m) 33b (c, i, & m) 66c (c, i, & m) 33a (c, i, & m) 33b (c, i, & m) - ql5840 - - 33a (c, i, & m) 33b (c, i, & m) 33a (c, i, & m) 33b (c, i, & m) 66c (c & i) 33a (c, i, & m) 33b (c, i, & m) 66c (c, i, & m) table 7: performance standards a a. performance standards for wo rst-case commercial conditions. function description s lowest s peed grade fastest s peed grade multiplexer 16:1 2.8 ns 2.4 ns parity tree 24 3.4 ns 2.9 ns 36 4.6 ns 3.9 ns counter 16 bit 275 mhz 328 mhz 32 bit 250 mhz 300 mhz synchronous fifo 128 x 32 197 mhz 235 mhz 128 x 64 188 mhz 266 mhz 256 x 16 208 mhz 248 mhz clock-to-out 6.5 ns 6 ns system clock 200 mhz 300 mhz ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 9 the ql58x0 device family logi c cell structure presented in figure 3 is a dual register, multiplexer-based logic cell. it is designed for wide fan-in and multiple, simu ltaneous output functions. both registers share clk, set, and reset inputs. the second register has a two-to-one multiplexer contro lling its input. the register can be loaded from the nz output or directly from a dedicated input. note: the input pp is not an ?input? in the classical sense. it is a static input to the logic cell and selects which path (nz or ps) is used as an input to the q2z register. all other inputs are dynamic and can be connected to multiple routing channels. the complete logic cell c onsists of two six-input and gates, four two-input and gates, seven two-to-one multiplexers, and two d flip-flops with asynchronous set and reset controls. the cell has a fan-in of 30 (including register control lines), fits a wide range of functions with up to 17 simultaneous inputs, and has six outputs (four combinatorial and two registered). the high logic capacity and fan-in of the logic cell accommodates many user functions with a single level of logic delay while other architectures require two or more levels of delay. figure 3: ql58x0 device family logic cell ram modules the ql58x0 device family includes up to 24 dual-port 2,304-bit ram modules for implementing ram, rom, and fifo functions. each module is user-configurable into two different block organizations and can be cascaded horizontally to increase their effective width, or vertically to in crease their effective depth as shown in figure 5 . qs a1 a2 a3 a4 a5 a6 os op b1 b2 c1 c2 ms d1 e1 n p e2 d2 n s f1 f3 f5 f6 f2 f4 ps pp mp az oz qz n z fz q2z qc qr www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 10 figure 4: 2,304-bit ram module the number of ram modules varies from 4 to 24 blocks for a total of 9.2 k to 55.3 k bits of ram. using the two ?mode? pins, designers can co nfigure each module into 128 x 18 and 256 x 9. the blocks are also easily cascadable to increase their effective width and/or depth (see figure 5 ) . figure 5: cascaded ram modules the ram modules are dual-port, with completely independent read and write ports and separate read and write clocks. the read ports support asynchro nous and synchronous operation, while the write ports support synchronous operation. each port has 18 da ta lines and 8 address lines, allowing word lengths of up to 18 bits and address spaces of up to 256 wo rds. depending on the mode selected, however, some higher order data or address lines may not be used. the write enable (we) line acts as a clock enable for synchronous write operation. the read enable (re) acts as a clock enable for synchronous read operation (a syncrd input low), or as a flow-through enable for asynchronous read operation (asyncrd input high). designers can cascade multiple ram modules to increase the depth or width allowed in single modules by connecting corresponding address lines together and dividing the words between modules. a similar technique can be used to cr eate depths greater than 256 words. in this case address signals higher than the msb are encoded onto the write enable (we) input for write operations. the read data outputs are multiplexed together using encoded higher re ad address bits for the multiplexer select signals. the ram blocks can be loaded with da ta generated internally (typically for ram or fifo functions) or with data from an external prom (typically for rom functions). mode[1:0] wa[7:0] wd[17:0] we wclk a syncrd ra[7:0] rd[17:0] re rclk wdata rdata rdata waddr wdata raddr ram module (2,304 bits) ram module (2,304 bits) ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 11 embedded computational unit (ecu) traditional programmable logic architec tures do not implement arithmetic fu nctions efficiently or effectively? these functions require high logic cell usage wh ile garnering only moderate performance results. the ql58x0 device family architecture allows for fu nctionality above and beyond that achievable using programmable logic devices. by embedding a dynamica lly reconfigurable computational unit, the ql58x0 device family can address various arithmetic functions efficiently. this approach offers greater performance and utilization than traditional programmable logic im plementations. the embedded block is implemented at the transistor level as shown in figure 6 . figure 6: ecu block diagram the ql58x0 device family ecu blocks ( table 8 ) are placed next to the sram circuitry for efficient memory/instruction fetch and addressing for dsp algorithmic implementations. up to twelve 8-bit mac functions ca n be implemented per cycle for a tota l of 1 billion macs/s when clocked at 100 mhz. additional multiply-a ccumulate functions can be implemented in the programmable logic. the modes for the ecu block are dynamically re -programmable through the programmable logic. table 8: ql58x0 device family ecu blocks device ecus ql5840 12 ql5820 0 ql5810 0 a[0:15] b[0:15] sign2 sign1 cin s1 s2 s3 a b c d 3-4 decoder 8-bit multiplier 16-bit adder 17-bit register 2-1 mux 2-1 mux 3-1 mux q[16:0] clk reset dq 00 01 10 a[7:0] a[15:8] www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 12 note: timing numbers in table 9 represent -8 worst case commercial conditions. table 9: ecu mode select criteria instruction operation ecu performance a , -8 wcc a. t pd , t su and t co do not include routing paths in/out of the ecu block. s 1 s 2 s3 t pd t s u t co 0 0 0 multiply 6.6 ns max 0 0 1 multiply-add 8.8 ns max 0 1 0 accumulate b b. internal feedback path in ecu re stricts max clk frequency to 238 mhz. 3.9 ns min 1.2 ns max 0 1 1 add 3.1 ns max 1 0 0 multiply (registered) c c. b [15:0] set to zero. 9.6 ns min 1.2 ns max 1 0 1 multiply- add (registered) 9.6 ns min 1.2 ns max 1 1 0 multiply - accumulate 9.6 ns min 1.2 ns max 1 1 1 add (registered) 3.9 ns min 1.2 ns max ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 1 3 phase locked loop (pll) information instead of requiring extra components, designers simply need to instantiate one of the pre-configured models (described in this section). the quic klogic built-in plls support a wider ra nge of frequencies than many other plls. these plls also have the abilit y to support different ranges of frequency multiplications or divisions, driving the device at a faster or slower rate than th e incoming clock frequency. when plls are cascaded, the clock signal must be routed off-chip through the pllpad_out pin prior to routing into another pll; internal routing cannot be used for cascading plls. figure 7 illustrates a quicklogic pll. figure 7: pll block diagram f in represents a very stable high-frequency input clock and produces an accurate signal reference. this signal can either bypass the pll entirely, thus entering the cl ock tree directly, or it can pass through the pll itself. within the pll, a voltage-controlled oscillator (vco) is added to the circuit. the external f in signal and the local vco form a control loop. the vco is multiplied or divided down to the reference frequency, so that a phase detector (the crossed circle in figure 7 ) can compare the two signals. if the phases of the external and local signals are not within the tolerance required, the phase detector sends a signal through the charge pump and loop filter ( figure 7 ). the charge pump generates an error voltage to bring the vco back into alignment, and the loop filter removes any high frequency noise before the error voltage enters the vco. this new vco signal enters the clock tree to drive the chip's circuitry. f out represents the clock signal emerging from the output pad (the output signal pllpad_out is explained in table 11 ). the pll always drives the pllpad_out signal , regardless of whether the pll is configured for on-chip use. the pllpad_out will not oscillate if p ll_reset is asserted, or if the pll is powered down. most quicklogic products contain four plls. the pll presented in figure 7 controls the clock tree in the fourth quadrant of its fpga. quicklog ic plls compensate for the additiona l delay created by the clock tree itself, as previously noted, by subtracting the clock tree delay thro ugh the feedback path. vco filter f in f out + - 1st quadrant 2nd quadrant 3rd quadrant 4th quadrant clock tree frequency divide frequency multiply 1 . _ . 2 . _ . 4 . _ . 4 . _ . 2 . _ . 1 . . _ pll bypass www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 14 pll modes of operation quicklogic plls have eight modes of operation, base d on the input frequency and desired output frequency? table 10 indicates the features of each mode. note: ?hf? stands for ?high frequency? and ?lf? stands for ?low frequency.? the input frequency can range from 12.5 mhz to 440 mh z, while output frequenc y ranges from 25 mhz to 220 mhz. when adding plls to the top-level design, be sure that the pll mode matches the desired input and output frequencies. pll s ignals table 11 summarizes the key signals in quicklogic plls. note: because pllclk_in and pll_reset signals have pll_inpad, and pllpad_out has outpad, you do not need to add additional pads to your design. table 10: pll mode frequencies pll model output frequency input frequency range output frequency range pll_hf same as input 66 mhz?220 mhz 66 mhz?220 mhz pll_lf same as input 25 mhz?66 mhz 25 mhz?66 mhz pll_mult2hf 2x 33 mhz?110 mhz 66 mhz?220 mhz pll_mult2lf 2x 12.5 mhz?33 mhz 25 mhz?66 mhz pll_div2hf 1/2x 220 mhz?440 mhz 110 mhz?220 mhz pll_div2lf 1/2x 50 mhz?220 mhz 25 mhz?110 mhz pll_mult4 4x 12.5 mhz?50 mhz 50 mhz?200 mhz pll_div4 1/4x 100 mhz?440 mhz 25 mhz?110 mhz table 11: quicklogic pll signals s ignal name description pllclk_in input clock signal pll_reset active high reset if pll_reset is assert ed, then clknet_out an d pllpad_out are reset to 0. this signal must be asserted and then released in order for the lock_detect to work. onn_offchip this is a reserved signal. it can be connected to vcc or gnd. clknet_out out to internal gates this signal bypasses the pll logic before driving the internal gates. note that this signal cannot be used in the same quadrant where the pll signal is used (pllclk_out). pllclk_out out from pll to internal gates this signal can drive the internal gates after going through the pll. pllpad_out out to off-chip this outgoing signal is used off-chip. the pllpad_out is always active, driving the pll-derived clock signal out through the pad. the pllpad_out will not oscillate if pll_reset is asserted, or if the pll is powered down. lock_detect active high lock detection signal note: for simulation purposes, this signal gets asserted after 10 clock cycles. however, it can take a maximum of 200 clock cycles to sync wi th the input cl ock upon release of the pll_reset signal. ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 15 i/o cell s tructure the ql58x0 device family features a variety of distinct i/o pins to maximize performance, functionality, and flexibility with bi-direction al i/o pins and input-only pins. all input and i/o pins are 1.8 v, 2.5 v, and 3.3 v tolerant and comply with the specific i/o standard selected. for single ended i/o standards, vccio specifies the input tolerance and the output drive. for voltage re ferenced i/o standards (e.g sstl), the voltage supplied to the inref pins in each bank specifies the input switch point. for example, the vccio pins must be tied to a 3.3 v supply to provide 3.3 v co mpliance. the ql58x0 device family can also support the lvds and lvpecl i/o standards with the use of external resistors (see table 12 ). as designs become more complex and requirements more stringent, several application-specific i/o standards have emerged for specific applications. i/o standa rds for processors, memori es, and a variety of bus applications have become commonplace and a requirem ent for many systems. in addition, i/o timing has become a greater issue with specific requirements fo r setup, hold, clock to out, and switching times. the ql58x0 device family has addressed these new system requirements and now includes a completely new i/o cell which consists of prog rammable i/os as well as a new cell structure consisting of three registers?input, output, and oe. the ql58x0 device family offers banks of programmable i/os that address many of the bus standards that are popular today. as shown in figure 8 each bi-directional i/o pin is as sociated with an i/o cell which features an input register, an input buffer, an output register, a three-st ate output buffer, an output enable register, and 2 two-to-one output multiplexers. table 12: i/o standards and applications i/o s tandard reference voltage output voltage application lvttl n/a 3.3 v general purpose lv c m o s 2 5 n/a 2.5 v general purpose lvcmos18 n/a 1.8 v general purpose pci n/a 3.3 v pci bus applications gtl+ 1 n/a backplane sstl3 1.5 3.3 v sdram sstl2 1.25 2.5 v sdram www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 16 figure 8: ql58x0 device family i/o cell the bi-directional i/o pin options can be programmed for input, output, or bi-directional operation. as shown in figure 8 , each bi-directional i/o pin is associated with an i/o cell which features an input register, an input buffer, an output register, a three-state output buffer, an output enable register, and 2 two-to-one multiplexers. the select lines of the two-to-one multiplexers are static and must be connected to either vcc or gnd. for input functions, i/o pins can prov ide combinatorial, registered data, or both options simultaneously to the logic array. for combinatorial input operation, data is routed from i/o pins through the input buffer to the array logic. for registered input operation, i/o pins driv e the d input of input cell re gisters, allowing data to be captured with fast, predictable se t-up times without consumin g internal logic cell resources. the comparator and multiplexer in the input path allo ws for native support of i/o standard s with reference points offset from traditional ground. for output functions, i/o pins can receive combinatorial or registered data from the logic array. for combinatorial output operation, data is routed from th e logic array through a multiplexer to the i/o pin. for registered output operation, the array logic drives the d input of the output cell regi ster which in turn drives the i/o pin through a multiplexer. the multiplexer allows either a combinatorial or a registered signal to be driven to the i/o pin. the addition of an output register will also decrease the tco. since the output register does not need to drive the routing the length of the output path is also reduced, and static timing analysis becomes very predictable. the three-state output buffer controls the flow of data from the array logic to the i/o pin and allows the i/o pin to act as an input and/or output. the buffer's output enable can be indi vidually controlled by the logic cell array or any pin (through the regular routing resources), or it can be bank-controlled through one of the global networks. the signal can also be either combinatorial or re gistered. this is identical to that of the flow for the output cell. for combinatorial control operation, data is routed from the logic array through a multiplexer to the three-state control. the ioctrl pins can directly dr ive the oe and clk signals fo r all i/o cells within the same bank. e r q d r q d e r q d + - pad output enable register output register input register ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 17 for registered control operation, the array logic drives th e d input of the oe cell register which in turn drives the three-state control through a multiplexer. the multip lexer allows either a combinatorial or a registered signal to be driven to the three-state control. when i/o pins are unused, the oe cont rols can be permanently disabled, allowing the output cell register to be used for registered feedback into the logic array. i/o cell registers are controlled by clock, clock enable , and reset signals, which can come from the regular routing resources, from one of the global networks, or from two ioctrl input pins per bank of i/o's. the clk and reset signals share common lines, while the cl ock enables for each regist er can be independently controlled. i/o interface support is programmable on a per bank basis. the two larger ql58x0 device s contain eight i/o banks. figure 9 illustrates the i/o bank configurations for ql5840. the two smaller ql58x0 devices contain two i/o banks per device. figure 10 illustrates the i/o bank configurations for ql5820 and ql5810. each i/o bank is independent of other i/o banks an d each i/o bank has its own vccio and inref supply inputs. a mixture of different i/o standards can be used on the device; however, there is a limitation as to which i/o standards can be supporte d within a given bank. only standa rds that share a common vccio and inref can be shared within the sa me bank (e.g., pci and lvttl). in the case of the ql5820 and ql5810, only one voltage-referenced standa rd can be used. the two i/o banks, a and b, share the inref pin. figure 9: multiple i/o banks on ql5840 embedded ram blocks pll pll fabric embeded computational units embedded ram blocks pll pll vccio(f) inref(f) vccio(e) inref(e) vccio(d) inref(d) vccio(c) inref (c) inref(b) vccio(b) inref(a) vccio(a) inref(h) vccio(h) inref(g) vccio(g) www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 18 figure 10: multiple i/o banks on ql5820 and 5810 programmable s lew rate each i/o has programmable slew rate capability?the slew rate can be ei ther fast or slow. the slower rate can be used to reduce the sw itching times of each i/o. programmable weak pull-down a programmable weak pull-down resistor is available on each i/o. the i/o weak pull-down eliminates the need for external pull down resi stors for used i/os as shown in figure 11 . the spec for pull-down current is maximum of 150 a under worst case condition. figure 11: programmable i/o weak pull-down embedded ram blocks fabric embedded ram blocks vccio(b) inref vccio(a) vded i/o output logic pa d ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 19 clock networks global clocks there are a maximum of seven global clock networks in each ql58x0 device. global clocks can drive logic cells and i/o registers, ecus, and ram blocks in the devi ce. all global clocks have access to a quad net (local clock network) connection with a programmable conne ction to the logic cell?s register clock input. figure 12: global clock architecture quad-net network there are five quad-net local clock networks in each qu adrant for a total of 20 in a device. each quad-net is local to a quadrant. before driving the column clock bu ffers, the quad-net is driven by the output of a mux which selects between the clk pin input and an internally generate d clock source (see figure 1 3 ). figure 13: global clock structure quad net clk pin global clock net t pgck t bgck internally generated clock, or clock from general routing network global clock (clk) input quad-net clock network ff global clock buffer www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 20 dedicated clock there is one dedicated clock in the larger device of the ql58x0 family (ql5840). this clock connects to the clock input of the logic cell and i/o registers, an d ram blocks through a hardwired connection and is multiplexed with the programmable clock input. the dedica ted clock provides a fast global network with low skew. users have the ability to select either the dedicated clock or the programmable clock ( figure 14 ). figure 14: dedicated clock circuitry within logic cell note: for more information on the clocking capabilitie s of the ql58x0 enhanced quickpci family, see quicklogic applicat ion note 68 at http://www.quicklogic.com /images/appnote68.pdf . i/o control and local hi-drives each bank of i/os has two input-only pins that can be programmed to drive the rst, clk, and en inputs of i/os in that bank. these input-only pins also serve as high drive inputs to a quadrant. these buffers can be driven by the internal logic both as an i/o control or high drive. for i/o constrained designs, these pins can be used for general purpose inputs. to provide more ge neral purpose i/os in the 208 pqfp package, the i/o controls pins are not bonded out. the performance of these resources is presented in table 1 3 . table 14 shows the total number of i/o control pins pe r device/package combination. these pins are not bonded out in the smaller devices and packages. this increas es the number of bi-directional user i/os available. table 13: i/o control network/local high-drive destination tt, 25 c, 2.5 v from pad from array i/o (far) 1.00 ns 1.14 ns i/o (near) 0.63 ns 0.78 ns skew 0.37 ns 0.36 ns table 14: i/o control pins per device/package combination device 144 tqfp 196 tfbga 208 pqfp 280 lfbga 484 bga ql5810----- ql5820 - - - - - ql5840 - - - 16 16 programmable clock or general routing dedicated clock clk logic cell ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 21 programmable logic routing ql58x0 devices are engineered with six types of rout ing resources as follows: short (sometimes called segmented) wires, dual wires, quad wires, express wire s, distributed networks, and default wires. short wires span the length of one logic cell, always in the vertic al direction. dual wires run horizontally and span the length of two logic cells. short and dual wires are pr edominantly used for local connections. default wires supply vcc and gnd (logic ?1? and logic ?0?) to each column of logic cells. quad wires have passive link interconne ct elements every fourth logic cell. as a result, these wires are typically used to implement intermediate length or medium fan-out nets. express lines run the length of the device uninterrupted . each of these lines has a higher capacitance than a quad, dual, or short wire, but less capacitance than shor ter wires connected to run the length of the device. the resistance will also be lower because the express wi res don't require the use of pass links. express wires provide higher performance for long routes or high fan-out nets. distributed networks are described in clock networks on page 19. these wires span the programmable logic and are driven by quad-net buffers. global power-on reset (por) the ql58x0 device family features a global power-on re set. this reset is hardwired to all registers and resets them to logic ?0? upon power-up of the device. in quic klogic devices, the asynchro nous reset input to flip- flops has priority over the set input; therefore, the glob al por will reset all flip-fl ops during power-up. if you want to set the flip-flops to logic ?1?, you must assert the ?set? signal after the global por signal has been deasserted. figure 15: power-on reset low power mode quiescent power consumption of all q l58x0 family devices can be reduced significantly by de-activating the charge pumps inside the architecture. by applying 3.3 v to the vpump pin, the internal charge pump is de- activated?this effectively reduces the static and dynamic power cons umption of the device. the ql58x0 device family is fully functional and operational in the low power mo de. users who have a 3.3 v supply available in their system should take advantage of this low power feature by tying the vpump pin to 3.3 v. otherwise, if a 3.3 v supply is not availabl e, this pin should be tied to ground. vcc power-on reset q xxxxxxx 0 www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 22 joint test access group (jtag) information figure 16: jtag block diagram microprocessors and application specific integrated circuits (asics) pose many design challenges, one problem being the accessibility of test points. jtag fo rmed in response to this ch allenge, resulting in ieee standard 1149.1, the standard test access port and boundary scan architecture. the jtag boundary scan test methodology allows complete observation and control of the boundary pins of a jtag-compatible device through jtag software. a test access port (tap) controller works in concert with the instruction register (ir), which allow users to run th ree required tests along with several user-defined tests. jtag tests allow users to reduce syst em debug time, reuse test platforms and tools, and reuse subsystem tests for fuller verification of higher level system elements. the 1149.1 standard requires the following three tests: ? extest instruction. the extest instruction performs a printed circuit board (pcb) interconnect test. this test places a device into an external boundary test mode, selecting the boundary scan register to be connected between the tap test data in (tdi) and te st data out (tdo) pins. boundary scan cells are preloaded with test patterns (through the sample/prelo ad instruction), and input boundary cells capture the input data for analysis. ? sample/preload instruction. the sample/preload instruction allows a device to remain in its functional mode, while selecting the boundary scan register to be connected between the tdi and tdo pins. for this test, the boundary scan register can be accessed thro ugh a data scan operation, allowing users to sample the functional data entering and leaving the device. tck tms trstb rdi tdo instruction decode & control logic tap controller state machine (16 states) instruction register boundary-scan register (data register) mux bypass register mux internal register i/o registers user defined data register ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 2 3 ? bypass instruction. the bypass instruction allows data to skip a device boundary scan entirely, so the data passes through the bypa ss register. the bypass instruction allows users to test a device without passing through other devices. the bypass register is connected between the tdi and tdo pins, allowing serial data to be transferred through a device withou t affecting the operation of the device. jtag b s dl s upport ? bsdl-boundary scan description language ? machine-readable data for test equipment to generate testing vectors and software ? bsdl files available for all device/p ackage combinations from quicklogic ? extensive industry support available and atvg (automatic test vector generation) s ecurity links there are several security links to disable reading logic from the array, and to disable jtag access to the device. programming these optional links completely disa bles access to the device from the outside world and provides an extra level of design security not possible in sram-based fpgas. the option to program these links is selectable through quickworks in the t ools/options/device programming window in spde?. power-up loading link the flexibility link enables power-up loading of the embedded ram blocks. if the link is programmed, the power-up loading state machine is activated during power-up of the device. the state machine communicates with an external eprom via the jtag pins to download memory contents into the on-chip ram. if the link is not programmed, power-up loadin g is not enabled and the jtag pins function as they normally would. the option to program this link is selectable throug h quickworks in the tools/options/device programming window in spde. for more information on power-up loading, see quicklogic application note 55 at http://www.quicklogic.com/images/appnote55.pdf . see the power-up loading power-up sequencing requirement for proper functionality in figure 17 . www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 24 figure 17: required power-up sequence when using power-up loading to use the power-up loading function in ql58x0, designers must ensure that v cc begins to ramp within a maximum of 2 ms of v ccio , v ded , v ded2 , and v pump . voltage v ccio v ded v ded2 v pump v cc time < 2 ms v cc ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 25 electrical s pecifications dc characteristics the dc specifications are provided in table 15 through table 19 . table 15: absolute maximum ratings parameter value parameter value vcc voltage -0.5 v to 2.0 v latch-up immunity 100 ma vccio voltage -0.5 v to 4.0 v dc input current 20 ma inref voltage 0.5 v to vccio leaded package storage temperature -65 c to + 150 c input voltage -0.5 v to vccio + 0.5 v laminate package (bga) storage temperature -55 c to + 125 c table 16: recommended operating range s ymbol parameter military industrial commercial unit min max min max min max vcc supply voltage 1.71 1.89 1.71 1.89 1.71 1.89 v vccio i/o input tolerance voltage 1.71 3.60 1.71 3.60 1.71 3.60 v tj junction temperature -55 125 -40 100 0 85 c k delay factor -33a speed grade 0.49 1.57 0.50 1.51 0.54 1.47 n/a -33b speed grade 0.48 1.40 0.50 1.34 0.53 1.31 n/a -66c speed grade 0.45 1.32 0.47 1.26 0.50 1.23 n/a www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 26 table 17: dc characteristics s ymbol parameter conditions min max units i l i or i/o input leakage current vi = vccio or gnd -1 1 a i oz 3-state output leakage current vi = vccio or gnd - 1 a c i i/o input capacitance - - 8 pf c clock clock input capacitance - - 8 pf i os output short circuit current a a. only one output at a time. du ration should not exceed 30 seconds. vo = gnd vo = vcc -15 40 -180 210 ma ma i ref quiescent current on inref - -10 10 a i pd current on programmable pull-down vcc = 1.8 v - 50 a i pump quiescent current on vpump vpump= 3.3 v - 10 a i pll quiescent current on each vccpll 2.5 v 3.3 v -3ma i vccio quiescent current on vccio vccio = 3.6 v vccio = 2.5 v vccio = 1.8 v - 20 10 10 a table 18: quiescent icc characteristics device vpump = 0 v vpump = 3 . 3 v ql5810 - - ql5820 - - ql5840 a, b a. for -33b/-66c commercial grade devices only. maximum quiescent icc is 3 ma for all industrial grade de vices and 5 ma for all military devices. b. quiescent icc is for current dr awn by vcc and vded. if any plls are used, see table 17 for current drawn by each pll. 2 ma - ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 27 figure 18 through figure 21 show the vil and vih characteristics for i/o and clock pins. figure 18: vil maximum for i/o table 19: dc input and output levels a a. the data provided in table 19 represents the jedec and pci specification. qu icklogic devices either meet or exceed these requirements. for data specif ic to quicklogic i/os, see table 20 through table 29 , figure 8 and figure 11 , and figure 3 9 through figure 42 . note: all clk, ioctrl, and pllin pins are clamped to th e vded rail. therefore, these pins can be driven up to vded. all jtag inputs are clamped to the vded2 rail. these jtag input pins can only be driven up to vded2. s ymbol inref v il v ih v ol v oh i ol i oh v min v ma x v min v max v min v max v max v min ma ma lvttl n/a n/a -0.3 0.8 2.2 vccio + 0.3 0.4 2.4 2.0 -2.0 lv c m o s 2 n/a n/a -0.3 0.7 1.7 vccio + 0.3 0.7 1.7 2.0 -2.0 lv c m o s 1 8 n/a n/a -0.3 0.63 1.2 vccio + 0.3 0.7 1.7 2.0 -2.0 gtl+ 0.88 1.12 -0.3 inref - 0.2 inref + 0.2 vccio + 0.3 0.6 n/a 40 n/a pci n/a n/a -0.3 0.3 x vccio 0.6 x v ccio vccio + 0.5 0.1 x vccio 0.9 x vccio 1.5 -0.5 sstl2 1.15 1.35 -0.3 inref - 0.18 inref + 0.18 vccio + 0.3 0.74 1.76 7.6 -7.6 sstl3 1.3 1.7 -0.3 inref - 0.2 inref + 0.2 vccio + 0.3 1.10 1.90 8 -8 vilmax for io 0 0.5 1 1.5 2 2.5 -55c -40c 0c 25c 70c 90c 110c 125c junction temperature voltage (v) 1.71 v 1.8 v 1.89 v 2.5 v 3.3 v 3.6 v www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 28 figure 19: vih minimum for i/o figure 20: vil maximum for clock pins vihmin for io 0 0.5 1 1.5 2 2.5 -55c -40c 0c 25c 70c 90c 110c 125c junction temperature voltage 1.71 v 1.8 v 1.89 v 2.5 v 3.3 v 3.6 v vilmax for clock pins 0 0.5 1 1.5 2 -55c -40c 0c 25c 70c 90c 110c 125c junction temperature voltage (v) 1.71v 1.8 v 1.89 v 2.5 v 3.3 v 3.6 v ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 29 figure 21: vih minimum for clock pins figure 22 through figure 26 show the output drive characteristics for the i/os across va rious voltages and temperatures. figure 22: drive current at vccio = 1.71 v vihmin for clock pins 0 0.5 1 1.5 2 2.5 -55c -40c 0c 25c 70c 90c 110c 125c junction temperature voltage (v) 1.71 v 1.8 v 1.89 v 2.5 v 3.3 v 3.6 v drive current @ vccio = 1.71 v 0 5 10 15 20 25 30 35 0 0.2 0 .4 0 .6 0 .8 1 1.2 1.4 1 .6 1. 71 output voltage (v) drive current (ma) ioh: -55c iol: -55c ioh: 25c iol: 25c ioh: 125c iol: 125c www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 3 0 figure 23: drive current at vccio = 1.8 v figure 24: drive current at vccio = 2.5 v drive current @ vccio = 1.8 v 0 5 10 15 20 25 30 35 40 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 output voltage (v) drive current (ma ) ioh: -55c iol: -55c ioh: 25c iol: 25c ioh: 125c iol: 125c drive current @ vccio = 2.5v 0 10 20 30 40 50 60 70 80 0 0.5 1 1.5 2 2.5 output voltage (v) drive current (ma) ioh: -55c iol: -55c ioh: 25c iol: 25c ioh: 125c iol: 125c ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 3 1 figure 25: drive current at vccio = 3.3 v figure 26: drive current at vccio = 3.6 v drive current @ vccio = 3.3v 0 20 40 60 80 100 120 0 0.5 1 1.5 2 2.5 3 3.3 output voltage (v) drive current (ma) ioh: -55c iol: -55c ioh: 25c iol: 25c ioh: 125c iol: 125c drive current @ vccio = 3.6v 0 20 40 60 80 100 120 140 0 0.5 1 1.5 2 2.5 3 3.3 3.6 output voltage (v) drive current (ma) ioh: -55c iol: -55c ioh: 25c iol: 25c ioh: 125c iol: 125c www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 3 2 figure 27 through figure 3 0 show the quiescent current for the ql5842 and ql5832 for each of the voltage supplies, across voltage and temp erature. quiescent current on v cc is a function of device utilization. the numbers in the following graphs were taken from 100% utilized designs. figure 27: quiescent current on v cc for ql5842 and ql5832 figure 28: quiescent current for ql5842 and ql5832 at v ded = 1.8 v quiescent current on vcc 0 100 200 300 400 500 600 700 800 -40c 0c 25c 70c 90c ambient temperature ua vcc=1.71v vcc=1.8v vcc=1.89v quiescent current on vded 0 5 10 15 20 25 -40c 0c 25c 70c 90c ambient temperature ua vded=1.71v vded=1.8v vded=1.89v ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 33 figure 29: quiescent current for ql5842 and ql5832 at v ded = 3.3 v figure 30: quiescent current for ql5842 and ql5832 at v ded = 2.5 v quiescent current on vded 0 5 10 15 20 25 30 35 40 45 -40c 0c 25c 70c 90c ambient temperature ua vded=3.3v vded=3.6v quiescent current on vded 0 5 10 15 20 25 -40c 0c 25c 70c 90c ambient temperature ua vded=2.5v www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 3 4 ac characteristics the ac specifications (at vcc = 1.8 v, ta = 25 c, worst case corner, speed grade = -8 (k = 1.01)) are provided from table 20 through table 29 . logic cell diagrams and wa veforms are provided from figure 3 1 through figure 42 . figure 31: ql58x0 device family logic cell table 20: logic cells s ymbol parameter value min max t pd combinatorial delay of the longest path: time taken by the combinatorial circuit to output 0.28 ns 0.98 ns t su setup time: time the synchronous input of t he flip-flop must be stable before the active clock edge 0.10 ns 0.25 ns t hl hold time: time the synchronous input of the flip-flop must be stable after the active clock edge 0 ns 0 ns t co clock-to-out delay: the amount of time ta ken by the flip-flop to output after the active clock edge. 0.22 ns 0.52 ns t cwhi clock high time: required minimum time the clock stays high 0.46 ns 0.46 ns t cwlo clock low time: required minimum time that the clock stays low 0.46 ns 0.46 ns t set set delay: time between when the flip-flop is ?set? (high) and when the output is consequently ?set? (high) 0.69 ns 0.69 ns t reset reset delay: time between when the flip-flop is ?reset? (low) and when the output is consequently ?reset? (low) 1.09 ns 1.09 ns t sw set width: time that the set signa l must remain high/low 0.3 ns 0.3 ns t rw reset width: time th at the reset signal must remain high/low 0.3 ns 0.3 ns ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 3 5 figure 32: logic cell flip-flop figure 33: logic cell flip-flop timings?first waveform figure 34: logic cell flip-flop timings?second waveform set d clk reset q set reset q clk t cwhi (min) t cwlo (min) t reset t rw t set t sw clk d q t su t hl t co www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 3 6 note: when using a pll, t pgck and t bgck are effectively zero due to delay adjustment by phase locked loop feedback path. figure 35: global clock structure timing elements figure 36: dual-port sram cell table 21: ql58x0 device family global clock delay clock s egment parameter value min max t pgck global clock pin delay to quad net - 1.92 ns t bgck global clock tree delay (quad net to flip-flop) - 0.28 ns t pgck t bgck internally generated clock, or clock from general routing network global clock (clk) input quad-net clock network ff global clock buffer wa wd we wclk re rclk ra rd ram module [9:0] [17:0] [9:0] [17:0] as yncr d ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 3 7 figure 37: ram cell synchronous write timing table 22: ram cell synchronous write timing s ymbol parameter value min max ram cell s ynchronous write timing t swa wa setup time to wclk: time the write address must be stable before the active edge of the write clock 0.47 ns - t hwa wa hold time to wclk: time the writ e address must be stable after the active edge of the write clock 0 ns - t swd wd setup time to wclk: time the write data must be stable before the active edge of the write clock 0.48 ns - t hwd wd hold time to wclk: time the write data must be stable after the active edge of the write clock 0 ns - t swe we setup time to wclk: time the writ e enable must be stable before the active edge of the write clock 0 ns - t hwe we hold time to wclk: time the wr ite enable must be stable after the active edge of the write clock 0 ns - t wcrd wclk to rd (wa = ra): time between the active write clock edge and the time when the data is available at rd - 3.79 ns t swa t swd t swe t hwa t hwd t hwe t wcrd old data new data wclk wa wd we rd www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 3 8 figure 38: ram cell synchronous and asynchronous read timing table 23: ram cell synchronous and asynchronous read timing s ymbol parameter value min max ram cell s ynchronous read timing t sra ra setup time to rclk: time the r ead address must be stable before the active edge of the read clock 0.43 ns - t hra ra hold time to rclk: time the read address must be stable after the active edge of the read clock 0 ns - t sre re setup time to wclk: time the read enable must be stable before the active edge of the read clock 0.21 ns - t hre re hold time to wclk: time the read enable must be stable after the active edge of the read clock 0 ns - t rcrd rclk to rd: time between the active read clock edge and the time when the data is available at rd - 2.25 ns ram cell asynchronous read timing r pdrd ra to rd: time between when the read address is input and when the data is output - 1.99 ns t sra t hra rclk ra t sre t hre t rcrd old data new data re rd r pdrd ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 3 9 figure 39: ql58x0 device family i/o cell output path figure 40: ql58x0 device family i/o cell output enable timing pad output register l h l h t outlh t outhl l h z t pzh l h z t pzl l h z t plz l h z t phz www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 40 table 24: ql58x0 device family i/o cell output timing s ymbol parameter value (ns) output register cell only min max t outlh output delay low to high (90% of h) - 2.95 t outhl output delay high to low (10% of l) - 2.49 t pzh output delay tri-state to high (90% of h) - 3.93 t pzl output delay tri-state to low (10% of l) - 2.84 t phz output delay high to tri-state - 3.62 t plz output delay low to tri-state - 3.4 t cop clock-to-out delay (does not include clock tree delays) - 3.3 (fast slew) 5.49 (slow slew) table 25: output slew rates @ vccio = 3.3 v, t = 25 c fast s lew s low s lew rising edge 2.8 v/ns 1.0 v/ns falling edge 2.86 v/ns 1.0 v/ns table 26: output slew rates @ vccio = 2.5 v, t = 25 c fast s lew s low s lew rising edge 1.7 v/ns 0.6 v/ns falling edge 1.9 v/ns 0.6 v/ns table 27: output slew rates @ vccio = 1.8 v, t = 25 c fast s lew s low s lew rising edge - - falling edge - - ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 41 figure 41: ql58x0 device family i/o cell input path figure 42: ql58x0 device family input register cell timing pad t isu t sid + - q e d r r clk d q tisu tih l tic o tiesu tieh tirst e icllii www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 42 table 28: i/o input register cell timing s ymbol parameter value min max t isu input register setup time: time the synchronous input of the flip-flop must be stable before the active clock edge 2.15 ns - t ihl input register hold time: time the synchronous input of the flip-fl op must be stable after the active clock edge 0 ns - t ico input register clock-to-out: time taken by the flip-flop to output after the active clock edge - 0.3 ns t irst input register reset delay: time between when the flip-flop is ?reset?(low) and when the output is consequently ?reset? (low) - 0.82 ns t iesu input register clock enable setup time: time ?enable? must be stable before the active clock edge 0.4 ns - t ieh input register clock enable hold time: time ?enable? must be stable after the active clock edge 0 ns - table 29: i/o input buffer delays s ymbol parameter value to get the total input delay add this delay to t i s u min max t sid (lvttl) lvttl input delay: low voltage ttl for 3.3 v applications - 0.82 ns t sid (lvcmos2) lvcmos2 input delay: low voltage cmos for 2.5 v and lower applications - 0.82 ns t sid (lvcmos18) lvcmos18 input delay: low voltage cmos for 1.8 v applications - - t sid (gtl+) gtl+ input delay: gunning transceiver logic - 0.94 ns t sid (sstl3) sstl3 input delay: stub series terminated logic for 3.3 v - 0.94 ns t sid (sstl2) sstl2 input delay: stub series terminated logic for 2.5 v - 0.94 ns ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 4 3 package thermal characteristics thermal resistance equations: jc = ( t j - t c )/p ja = ( t j - t a )/p p max = (t jmax - t amax ) / ja parameter description: jc : junction-to-case thermal resistance ja : junction-to-ambient thermal resistance t j : junction temperature t a : ambient temperature p: power dissipated by the device while operating p max : the maximum power dissipation for the device t jmax : maximum junction temperature t amax : maximum ambient temperature note: maximum junction temperature (t jmax ) is 125c. to calculate the maximum power dissipation for a device package look up ja from table 3 0 , pick an appropriate t amax and use: p max = (125oc - t amax )/ ja table 30: package thermal characteristics device package description ja (c/w) package code package type pin count 0 lfm 200 lfm 400 lfm ql5840 ps pbga 484 26.6 24.1 21.8 pt lfbga 280 34 31.6 29.9 pq pqfp 208 32 28 26.5 ql5820 pt lfbga 280 34 31.6 29.9 pq pqfp 208 43.6 41 39 pt tfbga 196 40 38 35.2 pftqfp144373634 ql5810 pt tfbga 196 54 51.8 48 pftqfp144413937 www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 44 kv and kt graphs figure 43: voltage factor vs. supply voltage figure 44: temperature factor vs. operating temperature voltage factor vs. supply voltage 0.94 0.96 0.98 1 1.02 1.04 1.06 1.95 1.89 1.85 1.8 1.75 1.71 1.65 supply voltage (v) kv kv temperature factor vs. operating temperature 0.8 0.85 0.9 0.95 1 1.05 1.1 1.15 1.2 -60 -55 -40 0 25 85 125 130 junction temperature (c) kt kt ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 45 power vs. operating frequency the basic power equation which best mo dels power consumption is given below: p total = 0.350 + f [0.0031 lc + 0.0948 ckbf + 0.01 clbf + 0.0263 ckld + 0.543 ram + 0.20 pll + 0.0035 inp + 0.0257 outp ] (mw) where: lc is the total number of logic cells in the design ckbf = # of clock buffers clbf = # of column clock buffers ckld = # of loads connected to the column clock buffers ram = # of ram blocks pll = # of plls inp is the number of input pins outp is the number of output pins note: to learn more about power consumption, see quicklogic application note 60 at http://www.quicklogic.com /images/appnote60.pdf . www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 46 power-up s equencing figure 45: power-up sequencing when powering up a device, the v cc /v ccio /v ded /v ded2 rails must take 400 s or longer to reach the maximum value (refer to figure 45 ). note: ramping v cc , v ccio , v pump , v ded , or v ded2 faster than 400 s can cause the device to behave improperly. for users with a limited power budget, ensure v ccio , v ded , v ded2 , and v pump are within 500 mv of v cc when ramping up the power supplies. voltage v ccio v ded v ded2 v pump v cc |v ccio , v ded , v ded2 , v pump - v cc | max time 400 us v cc ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 47 pin descriptions table 31: pin descriptions pin direction function description jtag pin descriptions tdi/rsi i test data in for jtag/ram init. serial data in hold high during normal operation. connects to serial prom data in for ram initialization. connect to vded2 if unused trstb/rro i/0 active low reset for jtag/ram init. reset out hold low during normal operation. connects to serial prom reset for ram initialization. connect to gnd if unused tms i test mode select for jtag hold high during normal operation. connect to vded2 if not used for jtag tck i test clock for jtag hold high or low during normal operation. connect to vded2 or gnd if not used for jtag tdo/rco o test data out for jtag/ram init. clock out connect to serial prom clock for ram initialization. must be left unconnected if not used for jtag or ram initialization. the output vo ltage drive is specified by vded. dedicated pin descriptions clk i global clock network pin low skew global clock. this pin provides access to a dedicated, distributed network capable of driving the clock, set, reset, f1, and a2 inputs to the logic cell, read, and write clocks, read and write enables of the embedded ram blocks, clock of the ecus, and output enables of the i/os. the voltage tolerance of this pin is specified by vded. i/o(a) i/o input/output pin the i/o pin is a bi-directional pin, configurable to either an input-only, output-only, or bi-directional pin. the a inside the parenthesis means that the i/o is located in bank a. if an i/o is not used, spde (quickworks tool) provides the option of tying that pin to gnd, vcc , or tristate. vcc i power supply pin connect to 1.8 v supply. vccio(a) i input voltage tolerance pin this pin provides the flexibility to interface the device with either a 3.3 v, 2.5 v, or 1.8 v device. the a inside the parenthesis means that vccio is located in bank a. every i/o pin in bank a will be tolerant of vccio input signals and will drive vccio level output signals. this pin must be connected to either 3.3 v, 2.5 v, or 1.8 v. vccio powers the the pllout pins. gnd i ground pin connect to ground. pllin i pll clock input clock input for pll. the voltage tolerance of this pin is specified by vded. www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 48 dedclk i dedicated clock pin very low skew global clock. this pin provides access to a dedicated, distributed clock network capable of driving the clock inputs of all sequential elements of the device (e.g., ram, flip flops). the voltage tolerance of this pin is specified by vded. gndpll i ground pin for pll connect to gnd. inref(a) i differential reference voltage the inref is the reference voltage pin for gtl+, sstl2, and sttl3 standards. follow the recommendations provided in table 19 for the appropriate standard. the a inside the parenthesis means that inref is located in bank a. this pin should be tied to gnd if voltage referenced standards are not used. pllout o pll output pin dedicated pll output pin. mu st be left unconnected if pll is powered up and not held in reset, since pllout will be driving the pll-derived clock. may be left unconnected if pll is held in reset or not powered up. pllout pin is driven by vccio. for a list of each pllout pin and the vccio pin that powers it see table 3 2 . ioctrl(a) i highdrive input this pin provides fast reset, set, clock, and enable access to the i/o cell flip-flops, providing fast clock-to-out and fast i/o response times. this pin can also double as a high-drive pin to the internal logic cells. the a inside the parent hesis means that ioctrl is located in bank a. there is an internal pulldown resistor to gnd on this pin. this pin should be tied to gnd if it is not used. for backwards compatibility with ql5632/ql5732, it can be tied to vded or gnd. if tied to vded, it will draw no more than 20 a per ioctrl pin due to current through the pulldown resistor. the voltage tolerance of this pin is specified by vded. note that the 208 pqfp package has no i/o control pins. vpump i charge pump disable this pin disables the internal charge pump for lower static power consumption. to disable the charge pump, connect vpump to 3.3 v. if the disable charge pump feature is not used, connect vpump to gnd. for backwards compatibility with ql5632/ql5732 devices, connect vpump to gnd. vded i voltage tolerance for clocks, tdo jtag output, and ioctrl this pin specifies the input voltage tolerance for clk, dedclk, pllin, and ioctrl dedicated input pins, as well as the output voltage drive tdo jtag pins. if the plls are used, vded must be the same as vccpll. the legal range for vded is between 1.71 v and 3.6 v. for backwards compatibility with ql5632/ql5732 devices, connect vded to 2.5 v. table 31: pin descriptions (continued) pin direction function description ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 49 vded2 i voltage tolerance for jtag pins (tdi, tms, tck, and trstb) these pins specify the input voltage tolerance for the jtag input pins. the legal range for vded2 is between 1.71 v and 3.6 v. t hese do not specify output voltage of the jtag output, tdo. refer to the vded pin section for specifying the jtag output voltage. vccpll i power supply pin for pll connect to 2.5 v or 3.3. v supply. for backwards compatibility with ql5632/q l5732 devices, connect to 2.5 v. to minimize static power consumption when designs do not utilize the plls, you may connect vccpll to gnd. if vccpll is grounded, the pll is disabled. pll_reset i pll reset pin if pll_reset is asserted , then clknet_out and pllpad_out are reset to 0. this signal must be asserted and then released in order for the lock_detect to work. if a pll module is not used, then the associated pllrst www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 50 figure 46: ql5840 i/o ba nks with relevant pins figure 47: ql5810 and ql5820 i/o banks with relevant pins io bank a io bank b v ccio (a) inref(a) ioctrl(a) io(a) v ccio (a) inref(a) ioctrl(a) io(a) io bank c io bank d v ccio (c) inref(c) ioctrl(c) io(c) v ccio (d) inref(d) ioctrl(d) io(d) io bank f io bank e v ccio (f) inref(f) ioctrl(f) io(f) v ccio (e) inref(e) ioctrl(e) io(e) io bank h io bank g (h) inref(h) ioctrl(h) io(h) v ccio v ccio (g) inref(g) ioctrl(g) io(g) v ccio (b io(b) (a) io(a) v ccio inref io bank a io bank b ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 51 recommended unused pin termin ations for ql58x0 device family all unused, general purpose i/o pins ca n be tied to vcc, gnd, or hiz (h igh impedance) inte rnally using the configuration editor. this option is given in the botto m-right corner of the placement window. to use the placement editor, choose constraint > fix placement in the option pull-down menu of spde. the rest of the pins should be terminated at the board level in the manner presented in table 33 . table 33: recommended unused pin terminations s ignal name recommended termination pllout www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 52 ql5810 - 144 tqfp pinout diagram pin 1 pin 37 pin 73 pin 109 ql5810-33bpf144c quickpci ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 5 3 ql5810 - 144 tqfp pinout table vccio(b) must be connected to vccio(pci) 3.3 v. summary: 47 pci pins, 54 user i/o, and 4 gclk. table 35: ql5810 - 144 tqfp pinout table pin function pin function pin function pin function 1 gnd 3 7 io(a) 7 3 io(a) 109 gnd 2 gnd 3 8 gnd 74 io(b) 110 cben(2) 3 io(a) 3 9 io(a) 75 gnd 111 vccio(b) 4 io(a) 40 vccio(a) 76 io(b) 112 framen 5 io(a) 41 io(a) 77 rstn 11 3 devseln 6 io(a) 42 io(a) 78 io(b) 114 trdyn 7 vcc 4 3 io(a) 79 vcc 115 irdyn 8 io(a) 44 io(a) 80 io(b) 116 stopn 9 io(a) 45 io(a) 81 ad(31) 117 perrn 10 io(a) 46 io(a) 82 inref 118 serrn 11 io(a) 47 io(a) 8 3 ad(30) 119 pa r 12 io(a) 48 io(a) 84 ad(29) 120 vcc 1 3 vccio(a) 49 vccio(a) 85 ad(28) 121 cben(1) 14 io(a) 50 io(a) 86 vccio(b) 122 vccio(b) 15 tdi 51 io(a) 87 ad(27) 12 3 ad(15) 16 clk(0) 52 vcc 88 ad(26) 124 ad(14) 17 clk(1) 5 3 trstb 89 ad(25) 125 vcc 18 vcc 54 vded2 90 (pci)clk 126 tck 19 io(a) 55 io(a) 91 clk(3) 127 vded2 20 vded 56 io(a) 92 vcc 128 ad(13) 21 io(a) 57 io(a) 9 3 clk(4) 129 ad(12) 22 io(a) 58 gnd 94 tms 1 3 0 gnd 2 3 gnd 59 io(a) 95 ad(24) 1 3 1 ad(11) 24 vccio(a) 60 vcc 96 gnd 1 3 2 ad(10) 25 io(a) 61 io(a) 97 vccio(b) 1 33 ad(9) 26 io(a) 62 io(a) 98 cben(3) 1 3 4 ad(8) 27 io(a) 6 3 io(a) 99 idsel 1 3 5 cben(0) 28 io(a) 64 io(a) 100 ad(23) 1 3 6 ad(7) 29 io(a) 65 io(a) 101 ad(22) 1 3 7 ad(6) 3 0 io(a) 66 io(a) 102 ad(21) 1 3 8 ad(5) 3 1 io(a) 67 io(a) 10 3 ad(20) 1 3 9 ad(4) 3 2 io(a) 68 io(a) 104 ad(19) 140 ad(3) 33 io(a) 69 vccio(a) 105 ad(18) 141 vccio(b) 3 4 tdo 70 io(a) 106 ad(17) 142 ad(2) 3 5 gnd 71 vpump 107 gnd 14 3 ad(1) 3 6 io(a) 72 io(a) 108 ad(16) 144 ad(0) www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 54 ql5810 - 196 tfbga pinout diagram top bottom quickpci ql5810-66cpt196c 1413121110987654321 a b c d e f g h j k l m n p pin a1 corner ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 55 ql5810 - 196 tfbga pinout table vccio(b) must be connected to vccio(pci) 3.3 v. summary: 47 pci pins, 78 user i/o, and 4 gclk. table 36: ql5810 - 196 tfbga pinout table ball function ball function ball function ball function ball function a1 ad(23) c1 3 io(a) f11 io(a) j9 gnd m7 vcc a2 cben(3) c14 io(a) f12 io(a) j10 gnd m8 io(a) a 3 ad(25) d1 stopn f1 3 io(a) j11 io(a) m9 io(a) a4 ad(27) d2 irdyn f14 io(a) j12 io(a) m10 io(a) a5 ad(24) d 3 ad(16) g1 ad(14) j1 3 io(a) m11 io(a) a6 ad(28) d4 idsel g2 tck j14 io(a) m12 io(a) a7 clk(4) d5 io(b) g 3 cben(1) k1 cben(0) m1 3 io(a) a8 clk(2) d6 vccio(b) g4 vcc k2 ad(6) m14 io(a) a9 ad(31) d7 vccio(b) g5 gnd k 3 ad(7) n1 io(b) a10 rstn d8 vded g6 gnd k4 io(b) n2 io(b) a11 inref d9 vccio(b) g7 gnd k5 vccio(b) n 3 io(a) a12 io(b) d10 io(b) g8 gnd k6 vccio(a) n4 io(a) a1 3 io(b) d11 io(b) g9 gnd k7 gnd n5 io(a) a14 io(b) d12 vpump g10 gnd k8 gnd n6 io(a) b1 ad(19) d1 3 io(a) g11 io(a) k9 vccio(a) n7 io(a) b2 ad(21) d14 io(a) g12 vcc k10 vccio(a) n8 io(a) b 3 ad(20) e1 serrn g1 3 io(a) k11 io(a) n9 io(a) b4 io(b) e2 perrn g14 io(a) k12 io(a) n10 io(a) b5 ad(26) e 3 framen h1 ad(11) k1 3 io(a) n11 io(a) b6 tms e4 cben(2) h2 ad(12) k14 io(a) n12 tdo b7 vcc e5 vccio(b) h 3 vded2 l1 ad(4) n1 3 io(a) b8 ad(30) e6 gnd h4 vccio(b) l2 ad(3) n14 io(a) b9 io(b) e7 gnd h5 gnd l 3 ad(5) p1 io(a) b10 io(b) e8 gnd h6 gnd l4 ad(0) p2 io(a) b11 io(b) e9 gnd h7 gnd l5 io(a) p 3 io(a) b12 io(b) e10 io(a) h8 gnd l6 io(a) p4 io(a) b1 3 io(a) e11 vccio(a) h9 gnd l7 vccio(a) p5 io(a) b14 io(a) e12 io(a) h10 gnd l8 vded p6 clk(0) c1 devseln e1 3 io(a) h11 vccio(a) l9 vded p7 clk(1) c2 ad(17) e14 vcc h12 trstb l10 vccio(a) p8 io(a) c 3 ad(18) f1 ad(15) h1 3 vded2 l11 vcc p9 io(a) c4 vcc f2 vcc h14 vcc l12 io(a) p10 io(a) c5 ad(22) f 3 trdyn j1 ad(10) l1 3 io(a) p11 io(a) c6 vcc f4 pa r j2 ad(9) l14 io(a) p12 io(a) c7 ad(29) f5 vccio(b) j 3 ad(8) m1 ad(2) p1 3 io(a) c8 (pci)clk f6 gnd j4 vcc m2 ad(1) p14 io(a) c9 io(b) f7 gnd j5 ad(13) m 3 io(a) c10 vcc f8 gnd j6 gnd m4 gnd c11 io(b) f9 gnd j7 gnd m5 vcc c12 io(a) f10 io(a) j8 gnd m6 tdi www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 56 ql5820 - 144 tqfp pinout diagram pin 1 pin 37 pin 73 pin 109 ql5820-33bpf144c quickpci ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 57 ql5820 - 144 tqfp pinout table vccio(b) must be connected to vccio(pci) 3.3 v. summary: 47 pci pins, 54 user i/o, and 4 gclk. table 37: ql5820 - 144 tqfp pinout table pin function pin function pin function pin function 1 gnd 3 7 io(a) 7 3 io(a) 109 gnd 2 gnd 3 8 gnd 74 io(b) 110 cben(2) 3 io(a) 3 9 io(a) 75 gnd 111 vccio(b) 4 io(a) 40 vccio(a) 76 io(b) 112 framen 5 io(a) 41 io(a) 77 rstn 11 3 devseln 6 io(a) 42 io(a) 78 io(b) 114 trdyn 7 vcc 4 3 io(a) 79 vcc 115 irdyn 8 io(a) 44 io(a) 80 io(b) 116 stopn 9 io(a) 45 io(a) 81 ad(31) 117 perrn 10 io(a) 46 io(a) 82 inref 118 serrn 11 io(a) 47 io(a) 8 3 ad(30) 119 pa r 12 io(a) 48 io(a) 84 ad(29) 120 vcc 1 3 vccio(a) 49 vccio(a) 85 ad(28) 121 cben(1) 14 io(a) 50 io(a) 86 vccio(b) 122 vccio(b) 15 tdi 51 io(a) 87 ad(27) 12 3 ad(15) 16 clk(0) 52 vcc 88 ad(26) 124 ad(14) 17 clk(1) 5 3 trstb 89 ad(25) 125 vcc 18 vcc 54 vded2 90 (pci)clk 126 tck 19 io(a) 55 io(a) 91 clk(3) 127 vded2 20 vded 56 io(a) 92 vcc 128 ad(13) 21 io(a) 57 io(a) 9 3 clk(4) 129 ad(12) 22 io(a) 58 gnd 94 tms 1 3 0 gnd 2 3 gnd 59 io(a) 95 ad(24) 1 3 1 ad(11) 24 vccio(a) 60 vcc 96 gnd 1 3 2 ad(10) 25 io(a) 61 io(a) 97 vccio(b) 1 33 ad(9) 26 io(a) 62 io(a) 98 cben(3) 1 3 4 ad(8) 27 io(a) 6 3 io(a) 99 idsel 1 3 5 cben(0) 28 io(a) 64 io(a) 100 ad(23) 1 3 6 ad(7) 29 io(a) 65 io(a) 101 ad(22) 1 3 7 ad(6) 3 0 io(a) 66 io(a) 102 ad(21) 1 3 8 ad(5) 3 1 io(a) 67 io(a) 10 3 ad(20) 1 3 9 ad(4) 3 2 io(a) 68 io(a) 104 ad(19) 140 ad(3) 33 io(a) 69 vccio(a) 105 ad(18) 141 vccio(b) 3 4 tdo 70 io(a) 106 ad(17) 142 ad(2) 3 5 gnd 71 vpump 107 gnd 14 3 ad(1) 3 6 io(a) 72 io(a) 108 ad(16) 144 ad(0) www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 58 ql5820 - 196 tfbga pinout diagram top bottom quickpci ql5820-66cpt196c 1413121110987654321 a b c d e f g h j k l m n p pin a1 corner ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 59 ql5820 - 196 tfbga pinout table vccio(b) must be connected to vccio(pci) 3.3 v. summary: 47 pci pins, 78 user i/o, and 4 gclk. table 38: ql5820 - 196 tfbga pinout table ball function ball function ball function ball function ball function a1 ad(23) c1 3 io(a) f11 io(a) j9 gnd m7 vcc a2 cben(3) c14 io(a) f12 io(a) j10 gnd m8 io(a) a 3 ad(25) d1 stopn f1 3 io(a) j11 io(a) m9 io(a) a4 ad(27) d2 irdyn f14 io(a) j12 io(a) m10 io(a) a5 ad(24) d 3 ad(16) g1 ad(14) j1 3 io(a) m11 io(a) a6 ad(28) d4 idsel g2 tck j14 io(a) m12 io(a) a7 clk(4) d5 io(b) g 3 cben(1) k1 cben(0) m1 3 io(a) a8 clk(2) d6 vccio(b) g4 vcc k2 ad(6) m14 io(a) a9 ad(31) d7 vccio(b) g5 gnd k 3 ad(7) n1 io(a) a10 rstn d8 vded g6 gnd k4 io(a) n2 io(a) a11 inref d9 vccio(b) g7 gnd k5 vccio(b) n 3 io(a) a12 io(b) d10 io(b) g8 gnd k6 vccio(a) n4 io(a) a1 3 io(b) d11 io(a) g9 gnd k7 gnd n5 io(a) a14 io(b) d12 vpump g10 gnd k8 gnd n6 io(a) b1 ad(19) d1 3 io(a) g11 io(a) k9 vccio(a) n7 io(a) b2 ad(21) d14 io(a) g12 vcc k10 vccio(a) n8 io(a) b 3 ad(20) e1 serrn g1 3 io(a) k11 io(a) n9 io(a) b4 io(b) e2 perrn g14 io(a) k12 io(a) n10 io(a) b5 ad(26) e 3 framen h1 ad(11) k1 3 io(a) n11 io(a) b6 tms e4 cben(2) h2 ad(12) k14 io(a) n12 tdo b7 vcc e5 vccio(b) h 3 vded2 l1 ad(4) n1 3 io(a) b8 ad(30) e6 gnd h4 vccio(b) l2 ad(3) n14 io(a) b9 io(b) e7 gnd h5 gnd l 3 ad(5) p1 io(a) b10 io(b) e8 gnd h6 gnd l4 ad(0) p2 io(a) b11 io(b) e9 gnd h7 gnd l5 io(a) p 3 io(a) b12 io(b) e10 io(b) h8 gnd l6 io(a) p4 io(a) b1 3 io(b) e11 vccio(a) h9 gnd l7 vccio(a) p5 io(a) b14 io(b) e12 io(a) h10 gnd l8 vded p6 clk(0) c1 devseln e1 3 io(a) h11 vccio(a) l9 vded p7 clk(1) c2 ad(17) e14 vcc h12 trstb l10 vccio(a) p8 io(a) c 3 ad(18) f1 ad(15) h1 3 vded2 l11 vcc p9 io(a) c4 vcc f2 vcc h14 vcc l12 io(a) p10 io(a) c5 ad(22) f 3 trdyn j1 ad(10) l1 3 io(a) p11 io(a) c6 vcc f4 pa r j2 ad(9) l14 io(a) p12 io(a) c7 ad(29) f5 vccio(b) j 3 ad(8) m1 ad(2) p1 3 io(a) c8 (pci)clk f6 gnd j4 vcc m2 ad(1) p14 io(a) c9 io(b) f7 gnd j5 ad(13) m 3 io(b) c10 vcc f8 gnd j6 gnd m4 gnd c11 io(b) f9 gnd j7 gnd m5 vcc c12 io(a) f10 io(a) j8 gnd m6 tdi www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 60 ql5820 - 208 pqfp pinout diagram top quickpci ql5820-66cpq208c ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 61 ql5820 - 208 pqfp pinout table vccio(b) must be connected to vccio(pci) 3.3 v. summary: 47 pci pins, 97 user i/o, and 4 gclk. table 39: ql5820 - 208 pqfp pinout table pin function pin function pin function pin function pin function pin function 1 i/o(a) 3 6 i/o(a) 71 i/o(a) 106 i/o(b) 141 ad(26) 176 pa r 2 i/o(a) 3 7 i/o(a) 72 vccio(a) 107 i/o(b) 142 ad(25) 177 vccio(b) 3 gnd 3 8 i/o(a) 7 3 i/o(a) 108 gnd 14 3 ad(24) 178 gnd 4 gnd 3 9 i/o(a) 74 i/o(a) 109 i/o(b) 144 cben(3) 179 cben(1) 5 i/o(a) 40 i/o(a) 75 gnd 110 i/o(b) 145 i/o(b) 180 ad(15) 6 i/o(a) 41 i/o(a) 76 vcc 111 vccio(b) 146 vcc 181 ad(14) 7 i/o(a) 42 i/o(a) 77 i/o(a) 112 i/o(b) 147 idsel 182 vcc 8 vccio(a) 4 3 i/o(a) 78 trstb 11 3 vcc 148 ad(23) 18 3 tck 9 i/o(a) 44 vccio(a) 79 vded2 114 i/o(b) 149 ad(22) 184 vded2 10 i/o(a) 45 i/o(a) 80 i/o(a) 115 i/o(b) 150 vccio(b) 185 ad(13) 11 i/o(a) 46 vcc 81 i/o(a) 116 i/o(b) 151 ad(21) 186 ad(12) 12 vcc 47 i/o(a) 82 i/o(a) 117 i/o(b) 152 ad(20) 187 ad(11) 1 3 i/o(a) 48 i/o(a) 8 3 gnd 118 inref 15 3 gnd 188 gnd 14 i/o(a) 49 gnd 84 vccio(a) 119 i/o(b) 154 ad(19) 189 vccio(b) 15 i/o(a) 50 tdo 85 i/o(a) 120 i/o(b) 155 i/o(b) 190 ad(10) 16 i/o(a) 51 i/o(a) 86 vcc 121 i/o(b) 156 gnd 191 ad(9) 17 i/o(a) 52 gnd 87 i/o(a) 122 vccio(b) 157 i/o(b) 192 ad(8) 18 i/o(a) 5 3 i/o(a) 88 i/o(a) 12 3 gnd 158 i/o(b) 19 3 cben(0) 19 vccio(a) 54 i/o(a) 89 vcc 124 rstn 159 i/o(b) 194 i/o(b) 20 i/o(a) 55 i/o(a) 90 i/o(a) 125 i/o(b) 160 gnd 195 vcc 21 gnd 56 vded 91 i/o(a) 126 i/o(b) 161 ad(18) 196 ad(7) 22 i/o(a) 57 i/o(a) 92 i/o(a) 127 i/o(b) 162 vccio(b) 197 ad(6) 2 3 tdi 58 gnd 9 3 i/o(a) 128 clk(2) 16 3 ad(17) 198 ad(5) 24 clk(0) 59 i/o(a) 94 i/o(a) 129 vded 164 ad(16) 199 ad(4) 25 clk(1) 60 vccio(a) 95 i/o(a) 1 3 0 clk(3) 165 vcc 200 ad(3) 26 vcc 61 i/o(a) 96 i/o(a) 1 3 1 vcc 166 cben(2) 201 ad(2) 27 i/o(a) 62 i/o(a) 97 i/o(a) 1 3 2 (pci)clk 167 framen 202 ad(1) 28 i/o(a) 6 3 i/o(a) 98 vccio(a) 1 33 tms 168 irdyn 20 3 vccio(b) 29 vded 64 i/o(a) 99 i/o(a) 1 3 4 ad(31) 169 trdyn 204 gnd 3 0 i/o(a) 65 i/o(a) 100 i/o(a) 1 3 5 ad(30) 170 i/o(b) 205 ad(0) 3 1 i/o(a) 66 i/o(a) 101 vpump 1 3 6 ad(29) 171 devseln 206 i/o(b) 3 2 i/o(a) 67 i/o(a) 102 i/o(a) 1 3 7 gnd 172 stopn 207 i/o(b) 33 gnd 68 i/o(a) 10 3 i/o(a) 1 3 8 vccio(b) 17 3 perrn 208 i/o(b) 3 4 vccio(a) 69 i/o(a) 104 gnd 1 3 9 ad(28) 174 serrn 3 5 i/o(a) 70 i/o(a) 105 i/o(b) 140 ad(27) 175 vcc www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 62 ql5820 - 280 lfbga pinout diagram top bottom quickpci ql5820-33bpt280c pin a1 corner ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 6 3 ql5820 - 280 lfbga pinout table vccio(b) must be connected to vccio(pci) (3.3 v). summary: 47 pci pins, 118 user i/o and 5 gclk. table 40: ql5820 - 280 lfbga pinout table ball function ball function ball function ball function ball function ball function a1 nc c10 i/o(b) e19 nc k16 i/o(a) r4 i/o(b) u1 3 i/o(a) a2 gnd c11 vccio(b) f1 nc k17 i/o(a) r5 gnd u14 nc a 3 ad(18) c12 i/o(b) f2 nc k18 i/o(a) r6 gnd u15 vccio(a) a4 ad(20) c1 3 i/o(b) f 3 serrn k19 trstb r7 vcc u16 i/o(a) a5 idsel c14 i/o(b) f4 devseln l1 ad(4) r8 vcc u17 tdo a6 nc c15 vccio(b) f5 gnd l2 ad(5) r9 gnd u18 nc a7 ad(26) c16 i/o(b) f15 vcc l 3 vccio(b) r10 gnd u19 i/o(a) a8 ad(30) c17 i/o(b) f16 nc l4 ad(6) r11 vcc v1 nc a9 rstn c18 i/o(b) f17 i/o(a) l5 vcc r12 vcc v2 gnd a10 clk(3) c19 i/o(b) f18 i/o(a) l15 gnd r1 3 vcc v 3 gnd a11 i/o(b) d1 trdyn f19 i/o(a) l16 i/o(a) r14 vded v4 i/o(a) a12 i/o(b) d2 irdyn g1 ad(14) l17 vccio(a) r15 gnd v5 i/o(a) a1 3 i/o(b) d 3 ad(16) g2 ad(15) l18 i/o(a) r16 i/o(a) v6 nc a14 nc d4 ad(23) g 3 nc l19 i/o(a) r17 vccio(a) v7 i/o(a) a15 i/o(b) d5 ad(24) g4 pa r m1 ad(0) r18 i/o(a) v8 i/o(a) a16 i/o(b) d6 ad(25) g5 vcc m2 ad(1) r19 i/o(a) v9 i/o(a) a17 i/o(b) d7 ad(29) g15 vcc m 3 ad(2) t1 i/o(b) v10 clk(1) a18 nc d8 i/o(b) g16 i/o(a) m4 ad(3) t2 i/o(b) v11 nc a19 nc d9 (pci) clk g17 i/o(a) m5 vcc t 3 i/o(a) v12 i/o(a) b1 nc d10 i/o(b) g18 i/o(a) m15 vded t4 i/o(a) v1 3 i/o(a) b2 nc d11 i/o(b) g19 i/o(a) m16 nc t5 i/o(a) v14 nc b 3 ad(19) d12 i/o(b) h1 ad(11) m17 i/o(a) t6 nc v15 i/o(a) b4 ad(21) d1 3 inref h2 ad(12) m18 i/o(a) t7 i/o(a) v16 i/o(a) b5 cben(3) d14 i/o(b) h 3 ad(13) m19 i/o(a) t8 i/o(a) v17 i/o(a) b6 nc d15 i/o(b) h4 cben(1) n1 nc t9 i/o(a) v18 gnd b7 ad(27) d16 i/o(a) h5 vcc n2 i/o(b) t10 i/o(a) v19 nc b8 ad(31) d17 i/o(a) h15 vcc n 3 i/o(b) t11 nc w1 nc b9 tms d18 i/o(a) h16 vded2 n4 i/o(b) t12 i/o(a) w2 nc b10 clk(2) d19 i/o(a) h17 i/o(a) n5 vcc t1 3 i/o(a) w 3 i/o(a) b11 i/o(b) e1 perrn h18 i/o(a) n15 vcc t14 i/o(a) w4 i/o(a) b12 i/o(b) e2 stopn h19 i/o(a) n16 i/o(a) t15 i/o(a) w5 i/o(a) b1 3 nc e 3 vccio(b) j1 ad(8) n17 i/o(a) t16 i/o(a) w6 i/o(a) b14 i/o(b) e4 framen j2 ad(9) n18 nc t17 nc w7 i/o(a) b15 i/o(b) e5 gnd j 3 vccio(b) n19 nc t18 i/o(a) w8 i/o(a) b16 i/o(b) e6 vcc j4 ad(10) p1 i/o(b) t19 i/o(a) w9 tdi b17 nc e7 vcc j5 gnd p2 i/o(b) u1 i/o(a) w10 i/o(a) b18 gnd e8 vded j15 vcc p 3 nc u2 i/o(a) w11 i/o(a) b19 nc e9 vcc j16 i/o(a) p4 nc u 3 nc w12 i/o(a) c1 cben(2) e10 gnd j17 vccio(a) p5 vcc u4 i/o(a) w1 3 i/o(a) c2 nc e11 gnd j18 i/o(a) p15 gnd u5 vccio(a) w14 nc c 3 ad(17) e12 vcc j19 i/o(a) p16 i/o(a) u6 nc w15 i/o(a) c4 ad(22) e1 3 vcc k1 vded2 p17 i/o(a) u7 i/o(a) w16 i/o(a) c5 vccio(b) e14 gnd k2 tck p18 i/o(a) u8 i/o(a) w17 i/o(a) c6 nc e15 vpump k 3 ad(7) p19 i/o(a) u9 vccio(a) w18 i/o(a) c7 ad(28) e16 i/o(a) k4 cben(0) r1 i/o(b) u10 clk(0) w19 nc c8 i/o(b) e17 vccio(a) k5 gnd r2 i/o(b) u11 vccio(a) c9 vccio(b) e18 nc k15 gnd r 3 vccio(b) u12 i/o(a) www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 64 ql5840 - 208 pqfp pinout diagram top quickpci ql5840-33bpq208c ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 65 ql5840 - 208 pqfp pinout table vccio(e), vccio(f), vccio(g), and vccio(h) must be connected to vccio(pci) 3.3 v. summary: 47 pci pins, 69 user i/o, and 8 gclk. table 41: ql5840 - 208 pqfp pinout table pin function pin function pin function pin function pin function pin function 1 pllrst(3) 3 6 i/o(b) 71 i/o(c) 106 vccpll(1) 141 ad(26) 176 pa r 2 vccpll(3) 3 7 i/o(b) 72 vccio(c) 107 i/o(e) 142 ad(25) 177 vccio(g) 3 gnd 3 8 i/o(b) 7 3 i/o(c) 108 gnd 14 3 ad(24) 178 gnd 4 gnd 3 9 i/o(b) 74 i/o(c) 109 i/o(e) 144 cben(3) 179 cben(1) 5 i/o(a) 40 inref(b) 75 gnd 110 i/o(e) 145 inref(f) 180 ad(15) 6 i/o(a) 41 i/o(b) 76 vcc 111 vccio(e) 146 vcc 181 ad(14) 7 i/o(a) 42 i/o(b) 77 i/o(c) 112 i/o(e) 147 idsel 182 vcc 8 vccio(a) 4 3 i/o(b) 78 trstb 11 3 vcc 148 ad(23) 18 3 tck 9 i/o(a) 44 vccio(b) 79 vded2 114 i/o(e) 149 ad(22) 184 vded2 10 i/o(a) 45 i/o(b) 80 i/o(d) 115 i/o(e) 150 vccio(f) 185 ad(13) 11 i/o(a) 46 vcc 81 i/o(d) 116 i/o(e) 151 ad(21) 186 ad(12) 12 vcc 47 i/o(b) 82 i/o(d) 117 i/o(e) 152 ad(20) 187 ad(11) 1 3 inref(a) 48 i/o(b) 8 3 gnd 118 inref(e) 15 3 gnd 188 gnd 14 i/o(a) 49 gnd 84 vccio(d) 119 i/o(e) 154 ad(19) 189 vccio(h) 15 i/o(a) 50 tdo 85 i/o(d) 120 i/o(e) 155 pllout(3) 190 ad(10) 16 i/o(a) 51 pllout(1) 86 vcc 121 i/o(e) 156 gndpll(0) 191 ad(9) 17 i/o(a) 52 gndpll(2) 87 i/o(d) 122 vccio(e) 157 gnd 192 ad(8) 18 i/o(a) 5 3 gnd 88 i/o(d) 12 3 gnd 158 vccpll(0) 19 3 cben(0) 19 vccio(a) 54 vccpll(2) 89 vcc 124 rstn 159 pllrst(0) 194 inref(h) 20 i/o(a) 55 pllrst(2) 90 i/o(d) 125 i/o(e) 160 gnd 195 vcc 21 gnd 56 vded 91 i/o(d) 126 i/o(e) 161 ad(18) 196 ad(7) 22 i/o(a) 57 i/o(c) 92 i/o(d) 127 clk(5) pllin(3) 162 vccio(g) 197 ad(6) 2 3 tdi 58 gnd 9 3 inref(d) 128 clk(6) 16 3 ad(17) 198 ad(5) 24 clk(0) 59 i/o(c) 94 i/o(d) 129 vded 164 ad(16) 199 ad(4) 25 clk(1) 60 vccio(c) 95 i/o(d) 1 3 0 clk(7) 165 vcc 200 ad(3) 26 vcc 61 i/o(c) 96 i/o(d) 1 3 1 vcc 166 cben(2) 201 ad(2) 27 clk(2) pllin(2) 62 i/o(c) 97 i/o(d) 1 3 2 (pci)clk 167 framen 202 ad(1) 28 clk(3) pllin(1) 6 3 i/o(c) 98 vccio(d) 1 33 tms 168 irdyn 20 3 vccio(h) 29 vded 64 i/o(c) 99 i/o(d) 1 3 4 ad(31) 169 trdyn 204 gnd 3 0 clk(4) pllin(0) 65 i/o(c) 100 i/o(d) 1 3 5 ad(30) 170 inref(g) 205 ad(0) 3 1 i/o(b) 66 i/o(c) 101 vpump 1 3 6 ad(29) 171 devseln 206 pllout(2) 3 2 i/o(b) 67 i/o(c) 102 pllout(0) 1 3 7 gnd 172 stopn 207 gnd 33 gnd 68 inref(c) 10 3 gnd 1 3 8 vccio(f) 17 3 perrn 208 gndpll(3) 3 4 vccio(b) 69 i/o(c) 104 gndpll(1) 1 3 9 ad(28) 174 serrn 3 5 i/o(b) 70 i/o(c) 105 pllrst(1) 140 ad(27) 175 vcc www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 66 ql5840 - 280 lfbga pinout diagram top bottom quickpci ql5840-33bpt280c pin a1 corner ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 67 ql5840 - 280 lfbga pinout table vccio(f), vccio(g) and vccio(h) must be connected to vccio(pci) (3.3 v). summary: 47 pci pins, 117 user i/o and 8 gclk. table 42: ql5840 - 280 lfbga pinout table ball function ball function ball function ball function ball function ball function a1 pllout(3) c10 clk(5)/ pllin(3) e19 ioctrl(d) k16 i/o(c) r4 i/o(h) u1 3 i/o(b) a2 gndpll(0) c11 vccio(e) f1 inref(g) k17 i/o(d) r5 gnd u14 ioctrl(b) a 3 ad(18) c12 i/o(e) f2 ioctrl(g) k18 i/o(c) r6 gnd u15 vccio(b) a4 ad(20) c1 3 i/o(e) f 3 serrn k19 trstb r7 vcc u16 i/o(b) a5 idsel c14 i/o(e) f4 devseln l1 ad(4) r8 vcc u17 tdo a6 ioctrl(f) c15 vccio(e) f5 gnd l2 ad(5) r9 gnd u18 pllrst(2) a7 ad(26) c16 i/o(e) f15 vcc l 3 vccio(h) r10 gnd u19 i/o(b) a8 ad(30) c17 i/o(e) f16 ioctrl(d) l4 ad(6) r11 vcc v1 pllout(2) a9 rstn c18 i/o(e) f17 i/o(d) l5 vcc r12 vcc v2 gndpll(3) a10 clk(7) c19 i/o(e) f18 i/o(d) l15 gnd r1 3 vcc v 3 gnd a11 i/o(e) d1 trdyn f19 i/o(d) l16 i/o(c) r14 vded v4 i/o(a) a12 i/o(e) d2 irdyn g1 ad(14) l17 vccio(c) r15 gnd v5 i/o(a) a1 3 i/o(e) d 3 ad(16) g2 ad(15) l18 i/o(c) r16 i/o(c) v6 ioctrl(a) a14 ioctrl(e) d4 ad(23) g 3 ioctrl(g) l19 i/o(c) r17 vccio(c) v7 i/o(a) a15 i/o(e) d5 ad(24) g4 pa r m1 ad(0) r18 i/o(c) v8 i/o(a) a16 i/o(e) d6 ad(25) g5 vcc m2 ad(1) r19 i/o(c) v9 i/o(a) a17 i/o(e) d7 ad(29) g15 vcc m 3 ad(2) t1 i/o(h) v10 clk(1) a18 pllrst(1) d8 i/o(f) g16 i/o(d) m4 ad(3) t2 i/o(h) v11 clk(4) dedclk/ pllin(0) a19 gnd d9 (pci) clk g17 i/o(d) m5 vcc t 3 i/o(a) v12 i/o(b) b1 pllrst(0) d10 i/o(e) g18 i/o(d) m15 vded t4 i/o(a) v1 3 i/o(b) b2 gnd d11 i/o(e) g19 i/o(d) m16 inref(c) t5 i/o(a) v14 inref(b) b 3 ad(19) d12 i/o(e) h1 ad(11) m17 i/o(c) t6 ioctrl(a) v15 i/o(b) b4 ad(21) d1 3 inref(e) h2 ad(12) m18 i/o(c) t7 i/o(a) v16 i/o(b) b5 cben(3) d14 i/o(e) h 3 ad(13) m19 i/o(c) t8 i/o(a) v17 i/o(b) b6 inref(f) d15 i/o(e) h4 cben(1) n1 ioctrl(h) t9 i/o(a) v18 gndpll(2) b7 ad(27) d16 i/o(d) h5 vcc n2 i/o(h) t10 i/o(a) v19 gnd b8 ad(31) d17 i/o(d) h15 vcc n 3 i/o(h) t11 clk(3/) pllin(1) w1 gnd b9 tms d18 i/o(d) h16 vded2 n4 i/o(h) t12 i/o(b) w2 pllrst(3) b10 clk(6) d19 i/o(d) h17 i/o(d) n5 vcc t1 3 i/o(b) w 3 i/o(a) b11 i/o(e) e1 perrn h18 i/o(d) n15 vcc t14 i/o(b) w4 i/o(a) b12 i/o(e) e2 stopn h19 i/o(d) n16 i/o(c) t15 i/o(b) w5 i/o(a) b1 3 ioctrl(e) e 3 vccio(g) j1 ad(8) n17 i/o(c) t16 i/o(b) w6 i/o(a) b14 i/o(e) e4 framen j2 ad(9) n18 ioctrl(c) t17 vccpll(2) w7 i/o(a) b15 i/o(e) e5 gnd j 3 vccio(g) n19 ioctrl(c) t18 i/o(b) w8 i/o(a) b16 i/o(e) e6 vcc j4 ad(10) p1 i/o(h) t19 i/o(b) w9 tdi b17 vccpll(1) e7 vcc j5 gnd p2 i/o(h) u1 i/o(a) w10 clk(2)/ pllin(2) b18 gndpll(1) e8 vded j15 vcc p 3 ioctrl(h) u2 i/o(a) w11 i/o(b) b19 pllout(0) e9 vcc j16 i/o(c) p4 inref(h) u 3 vccpll(3) w12 i/o(b) c1 cben(2) e10 gnd j17 vccio(d) p5 vcc u4 i/o(a) w1 3 i/o(b) c2 vccpll(0) e11 gnd j18 i/o(d) p15 gnd u5 vccio(a) w14 ioctrl(b) c 3 ad(17) e12 vcc j19 i/o(d) p16 i/o(c) u6 inref(a) w15 i/o(b) c4 ad(22) e1 3 vcc k1 vded2 p17 i/o(c) u7 i/o(a) w16 i/o(b) c5 vccio(f) e14 gnd k2 tck p18 i/o(c) u8 i/o(a) w17 i/o(b) c6 ioctrl(f) e15 vpump k 3 ad(7) p19 i/o(c) u9 vccio(a) w18 i/o(b) c7 ad(28) e16 i/o(d) k4 cben(0) r1 i/o(h) u10 clk(0) w19 pllout(1) c8 i/o(f) e17 vccio(d) k5 gnd r2 i/o(h) u11 vccio(b) c9 vccio(f) e18 inref(d) k15 gnd r 3 vccio(h) u12 i/o(b) www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 68 ql5840 - 484 pbga pinout diagrams top bottom quickpci ql5840-66cps484c 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 a b c e d f g h k j l m n r p t u v y w 22 21 a b aa pin a1 corner ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 69 ql5840 - 484 pbga pinout table table 43: ql5840 - 484 pbga pinout table ball function ball function ball function ball function ball function ball function a1 i/o(a) c17 i/o(g) f11 vccio(h) j5 i/o(a) l21 i/o(f) p15 vded a2 pllrst(3) c18 ad(18) f12 vccio(g) j6 i/o(a) l22 i/o(f) p16 i/o(e) a 3 i/o(a) c19 ad(23) f1 3 ad(12) j7 i/o(a) m1 i/o(b) p17 i/o(e) a4 i/o(a) c20 gndpll(0) f14 vccio(pci) j8 vcc m2 i/o(b) p18 i/o(e) a5 i/o(a) c21 ad(27) f15 n/c j9 gnd m 3 i/o(b) p19 i/o(e) a6 i/o(h) c22 ad(30) f16 vccio(g) j10 vcc m4 clk(3)/ pllin(1) p20 i/o(e) a7 i/o(h) d1 i/o(a) f17 n/c j11 vcc m5 i/o(b) p21 i/o(e) a8 ioctrl(h) d2 i/o(a) f18 i/o(f) j12 gnd m6 vccio(b) p22 i/o(e) a9 ad(0) d 3 i/o(a) f19 i/o(f) j1 3 vcc m7 clk(1) r1 i/o(b) a10 n/c d4 i/o(a) f20 ioctrl(f) j14 gnd m8 vcc r2 inref(b) a11 n/c d5 i/o(a) f21 i/o(f) j15 vcc m9 vcc r 3 i/o(b) a12 tck d6 i/o(h) f22 ioctrl(f) j16 ad(29) m10 gnd r4 i/o(b) a1 3 ad(10) d7 i/o(h) g1 i/o(a) j17 vccio(f) m11 gnd r5 i/o(b) a14 ad(13) d8 i/o(h) g2 i/o(a) j18 i/o(f) m12 gnd r6 i/o(b) a15 serrn d9 i/o(h) g 3 i/o(a) j19 i/o(f) m1 3 gnd r7 i/o(b) a16 i/o(g) d10 ad(4) g4 i/o(a) j20 i/o(f) m14 gnd r8 gnd a17 irdyn d11 ad(7) g5 i/o(a) j21 i/o(f) m15 gnd r9 vcc a18 ad(17) d12 ad(8) g6 i/o(a) j22 i/o(f) m16 gnd r10 vcc a19 ad(20) d1 3 ad(14) g7 gnd k1 tdi m17 i/o(e) r11 gnd a20 gnd d14 cben(1) g8 i/o(h) k2 i/o(a) m18 i/o(e) r12 vded a21 pllout(3) d15 ioctrl(g) g9 i/o(h) k 3 i/o(a) m19 i/o(e) r1 3 vcc a22 idsel d16 cben(2) g10 i/o(h) k4 i/o(a) m20 clk(7) r14 vcc b1 i/o(a) d17 ad(16) g11 cben(0) k5 i/o(a) m21 clk(5)/ pllin(3) r15 gnd b2 gnd d18 ad(22) g12 gnd k6 vccio(a) m22 tms r16 i/o(d) b 3 gndpll(3) d19 vccpll(0) g1 3 i/o(g) k7 i/o(a) n1 i/o(b) r17 vccio(e) b4 gnd d20 ad(26) g14 i/o(g) k8 vcc n2 i/o(b) r18 i/o(e) b5 i/o(a) d21 ad(31) g15 pa r k9 vcc n 3 i/o(b) r19 i/o(e) b6 i/o(h) d22 rstn g16 vpump k10 gnd n4 i/o(b) r20 i/o(e) b7 i/o(h) e1 ioctrl(a) g17 vccio(f) k11 gnd n5 i/o(b) r21 i/o(e) b8 inref(h) e2 i/o(a) g18 i/o(f) k12 gnd n6 i/o(b) r22 i/o(e) b9 i/o(h) e 3 i/o(a) g19 i/o(f) k1 3 gnd n7 i/o(b) t1 i/o(b) b10 ad(3) e4 i/o(a) g20 i/o(f) k14 vcc n8 vcc t2 i/o(b) b11 ad(6) e5 i/o(a) g21 inref(f) k15 vcc n9 vcc t 3 i/o(b) b12 n/c e6 i/o(h) g22 i/o(f) k16 i/o(f) n10 gnd t4 i/o(b) b1 3 n/c e7 n/c h1 i/o(a) k17 i/o(f) n11 gnd t5 i/o(b) b14 n/c e8 i/o(h) h2 i/o(a) k18 i/o(f) n12 gnd t6 vccio(b) b15 i/o(g)) e9 i/o(h) h 3 i/o(a) k19 i/o(f) n1 3 gnd t7 gnd b16 devseln e10 ad(5) h4 i/o(a) k20 i/o(f) n14 vcc t8 i/o(c) b17 framen e11 vded2 h5 ioctrl(a) k21 i/o(f) n15 vcc t9 n/c b18 ad(19) e12 ad(9) h6 vccio(a) k22 i/o(f) n16 i/o(e) t10 trstb b19 pllrst(0) e1 3 ad(15) h7 i/o(h) l1 clk(4) dedclk/ pllin(0) n17 vccio(e) t11 gnd b20 cben(3) e14 i/o(g) h8 gnd l2 clk(0) n18 i/o(e) t12 n/c b21 ad(24) e15 ioctrl(g) h9 vcc l 3 clk(2)/ pllin(2) n19 i/o(e) t1 3 i/o(d) b22 ad(28) e16 stopn h10 vcc l4 i/o(a) n20 i/o(e) t14 n/c c1 i/o(a) e17 inref(g) h11 vded l5 i/o(a) n21 i/o(e) t15 i/o(d) c2 i/o(a) e18 i/o(g) h12 gnd l6 i/o(a) n22 i/o(e) t16 gnd c 3 vccpll(3) e19 ad(25) h1 3 vcc l7 gnd p1 i/o(b) t17 i/o(e) www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 70 vccio(f) and vccio(g) must be connected to vccio(pci) (3.3 v). summary: 47 pci pins, 264 us er i/o, and 8 gclk. c4 pllout(2) e20 i/o(f) h14 vcc l8 gnd p2 i/o(b) t18 i/o(e) c5 i/o(a) e21 i/o(f) h15 gnd l9 gnd p 3 i/o(b) t19 i/o(e) c6 i/o(h) e22 i/o(f) h16 ad(21) l10 gnd p4 i/o(b) t20 i/o(e) c7 i/o(h) f1 i/o(a) h17 i/o(f) l11 gnd p5 i/o(b) t21 ioctrl(e) c8 i/o(h) f2 inref(a) h18 i/o(f) l12 gnd p6 vccio(b) t22 i/o(e) c9 ioctrl(h) f 3 i/o(a) h19 i/o(f) l1 3 gnd p7 i/o(b) u1 ioctrl(b) c10 i/o(h) f4 i/o(a) h20 i/o(f) l14 vcc p8 vcc u2 i/o(b) c11 ad(2) f5 i/o(a) h21 i/o(f) l15 vcc p9 gnd u 3 ioctrl(b) c12 i/o(h) f6 vccio(a) h22 i/o(f) l16 clk(6) p10 vcc u4 i/o(b) c1 3 ad(11) f7 vccio(h) j1 i/o(a) l17 vccio(f) p11 gnd u5 i/o(b) c14 i/o(g) f8 i/o(h) j2 i/o(a) l18 i/o(f) p12 vcc u6 i/o(c) c15 perrn f9 vccio(h) j 3 i/o(a) l19 (pci)clk p1 3 vcc u7 vccio(c) c16 trdyn f10 ad(1) j4 i/o(a) l20 i/o(f) p14 gnd u8 n/c u9 vccio(c) v8 i/o(c) w7 n/c y6 i/o(c) aa5 i/o(c) ab4 i/o(b) u10 i/o(c) v9 n/c w8 i/o(c) y7 i/o(c) aa6 i/o(c) ab5 i/o(b) u11 vccio(c) v10 i/o(c) w9 i/o(c) y8 ioctrl(c) aa7 i/o(c) ab6 i/o(c) u12 vccio(d) v11 i/o(c) w10 i/o(c) y9 i/o(c) aa8 inref(c) ab7 i/o(c) u1 3 i/o(d) v12 vded2 w11 i/o(c) y10 i/o(c) aa9 i/o(c) ab8 ioctrl(c) u14 vccio(d) v1 3 n/c w12 i/o(d) y11 i/o(d) aa10 i/o(c) ab9 i/o(c) u15 n/c v14 i/o(d) w1 3 i/o(d) y12 i/o(d) aa11 i/o(c) ab10 i/o(c) u16 vccio(d) v15 i/o(d) w14 i/o(d) y1 3 i/o(d) aa12 i/o(d) ab11 i/o(c) u17 vccio(e) v16 inref(d) w15 i/o(d) y14 i/o(d) aa1 3 i/o(d) ab12 i/o(d) u18 i/o(e) v17 i/o(d) w16 n/c y15 ioctrl(d) aa14 i/o(d) ab1 3 i/o(d) u19 i/o(e) v18 i/o(e) w17 i/o(d) y16 i/o(d) aa15 i/o(d) ab14 i/o(d) u20 ioctrl(e) v19 i/o(e) w18 i/o(e) y17 i/o(d) aa16 i/o(d) ab15 i/o(d) u21 i/o(e) v20 i/o(e) w19 i/o(e) y18 i/o(e) aa17 i/o(d) ab16 ioctrl(d) u22 inref(e) v21 i/o(e) w20 i/o(e) y19 pllout(0) aa18 i/o(d) ab17 i/o(d) v1 i/o(b) v22 i/o(e) w21 i/o(e) y20 pllrst(1) aa19 i/o(e) ab18 i/o(d) v2 i/o(b) w1 i/o(b) w22 i/o(e) y21 i/o(e) aa20 gndpll(1) ab19 i/o(e) v 3 i/o(b) w2 i/o(b) y1 i/o(b) y22 i/o(e) aa21 i/o(e) ab20 gnd v4 i/o(b) w 3 i/o(b) y2 i/o(b) aa1 tdo aa22 i/o(e) ab21 vccpll(1) v5 i/o(b) w4 i/o(b) y 3 vccpll(2) aa2 pllout(1) ab1 i/o(b) ab22 i/o(e) v6 i/o(c) w5 i/o(b) y4 i/o(c) aa 3 gnd ab2 gndpll(2) v7 i/o(c) w6 i/o(c) y5 i/o(c) aa4 i/o(b) ab 3 pllrst(2) table 43: ql5840 - 484 pbga pinout table (continued) ball function ball function ball function ball function ball function ball function ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 71 package mechanical drawings www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 72 144 tqfp packaging drawing ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 7 3 144 tqfp packaging drawing (continued) www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 74 196 tfbga packaging drawing ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 75 208 pqfp packaging drawing www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 76 280 lfbga packaging drawing ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 77 484 pbga packaging drawing www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 78 packaging information the ql58x0 device family product pack aging information is presented in table 44 . note: military temperature range plastic packages will be added as follow on products to the commercial and industrial products. ordering information table 44: packaging options device information device ql5810 ql5820 ql5840 pin pitch pin pitch pin pitch package definitions a a. pqfp = plastic quad flat pack pbga = plastic ball grid array tfbga = thin fine pitch ball grid array lfbga = low profile fine pitch ball grid array tqfp = thin quad flat pack 144 tqfp 0.50 mm 144 tqfp 0.50 mm 208 pqfp 0.50 mm 196 tfbga 0.80 mm 196 tfbga 0.80 mm 280 lfbga 0.80 mm 208 pqfp 0.50 mm 484 pbga 1.00 mm 280 lfbga 0.80 mm ql 5 8 x0 - 33 bp s 4 8 4c oper a ting r a nge: c = commerci a l i = ind us tri a l m = milit a ry p a ck a ge le a d co u nt: pf144 (pfn144)* = 144-pin tqfp (0.5 mm) pt196 (ptn196)* = 196- ba ll tfbga (0. 8 mm) pq20 8 (pqn20 8 )* = 20 8 -pin pqfp (0.5 mm) pt2 8 0 (ptn2 8 0)* = 2 8 0- ba ll lfbga (0. 8 mm) p s 4 8 4 (p s n4 8 4)* = 4 8 4- ba ll pbga (1.0 mm) p a rt n u m b er: 5 8 40, 5 8 20, 5 8 10 q u icklogic device s peed gr a de: - 33 a = 33 mhz pci, s t a nd a rd fpga - 33 b = 33 mhz pci, f as t fpga -66c = 66 mhz pci, f as te s t fpga * le a d-free p a ck a ging i s a v a il ab le, cont a ct q u icklogic reg a rding a v a il ab ility ( s ee cont a ct inform a tion). ? 2006 quicklogic corporation www.quicklogic.com ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 79 contact information phone: (408) 990-4000 (us) (905) 940-4149 (canada) +(44) 1932 57 9011 (europe ? except german y/benelux) +(49) 89 930 86 170 (germany/benelux) +(86) 21 6867 0273 (asia ? except japan) +(81) 45 470 5525 (japan) e-mail: info@quicklogic.com sales: www.quicklogic.com/sales support: www.quicklogic.com/support internet: www.quicklogic.com revision history revisio n date comments a october 2003 wai-leng lim and kathleen murchek b november 2003 bernhard andretzky and kathleen murchek updated figure 1. block diagram c december 2003 bernhard andretzky and kathleen murchek d march 2004 bernhard andretzky and kathleen murchek changed ram information and made minor updates. e june 2004 bernhard andretzky and kathleen murchek updated performance standards table and remo ved military from ordering information. updated ac characteristics tables values. updated pll descriptions. f july 2004 bernhard andretzky and kathleen murchek g august 2004 bernhard andretzky and kathleen murchek updated pin tables. h november 2004 bernhard andretzky and kathleen murchek updated pin tables. i march 2005 bernhard andretzky, mehul kochar and kathleen murchek added ql5820 - 280 device. removed all ql5830 devices. updated pll information. added lead-free packaging information. in the packaging information section, the pitch for the ql5810- and ql5822-196 tfbga was corrected from 0.05 mm to 0.08 mm. j june 2005 mehul kochar and kathleen murchek added table 6: device speed grade and operating range package availability. k february 2006 mehul kochar and kathleen murchek added 484 lead-free packaging to ordering information section. added page 2 of 144-pin package drawing. l may 2006 kathleen murchek replaced pages 1 and 2 of 144-pin package drawing. www.quicklogic.com ? 2006 quicklogic corporation ? ? ? ? ? ? ql58x0 enhanced quickpci? target family data sheet rev. l 80 copyright and trademark information copyright ? 2006 quicklogic corpor ation. all rights reserved. the information contained in this document is protected by copyright. all righ ts are reserved by quicklogic corporation. quickl ogic corporation reserves the right to modify this document without an y obligation to notify any person or entity of such revision. copying, duplicating, selling, or otherwis e distributing any part of this product without the prior written consent of an authorized rep resentative of quicklogic is prohibited. quicklogic and the quicklogic logo, quickpci and quickworks are registered trademarks of quic klogic corporation; spde is a trademark of quicklogic corporation. |
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